393 lines
8.7 KiB
C
393 lines
8.7 KiB
C
/*
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* arch/arm/mach-spear3xx/clock.c
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*
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* SPEAr3xx machines clock framework source file
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <mach/misc_regs.h>
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#include <plat/clock.h>
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/* root clks */
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/* 32 KHz oscillator clock */
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static struct clk osc_32k_clk = {
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.flags = ALWAYS_ENABLED,
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.rate = 32000,
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};
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/* 24 MHz oscillator clock */
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static struct clk osc_24m_clk = {
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.flags = ALWAYS_ENABLED,
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.rate = 24000000,
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};
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/* clock derived from 32 KHz osc clk */
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/* rtc clock */
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static struct clk rtc_clk = {
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.pclk = &osc_32k_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = RTC_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* clock derived from 24 MHz osc clk */
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/* pll1 configuration structure */
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static struct pll_clk_config pll1_config = {
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.mode_reg = PLL1_CTR,
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.cfg_reg = PLL1_FRQ,
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};
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/* PLL1 clock */
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static struct clk pll1_clk = {
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.pclk = &osc_24m_clk,
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.en_reg = PLL1_CTR,
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.en_reg_bit = PLL_ENABLE,
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.recalc = &pll1_clk_recalc,
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.private_data = &pll1_config,
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};
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/* PLL3 48 MHz clock */
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static struct clk pll3_48m_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &osc_24m_clk,
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.rate = 48000000,
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};
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/* watch dog timer clock */
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static struct clk wdt_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &osc_24m_clk,
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.recalc = &follow_parent,
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};
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/* clock derived from pll1 clk */
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/* cpu clock */
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static struct clk cpu_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &pll1_clk,
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.recalc = &follow_parent,
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};
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/* ahb configuration structure */
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static struct bus_clk_config ahb_config = {
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.reg = CORE_CLK_CFG,
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.mask = PLL_HCLK_RATIO_MASK,
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.shift = PLL_HCLK_RATIO_SHIFT,
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};
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/* ahb clock */
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static struct clk ahb_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &pll1_clk,
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.recalc = &bus_clk_recalc,
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.private_data = &ahb_config,
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};
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/* uart configurations */
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static struct aux_clk_config uart_config = {
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.synth_reg = UART_CLK_SYNT,
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};
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/* uart parents */
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static struct pclk_info uart_pclk_info[] = {
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{
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.pclk = &pll1_clk,
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.pclk_mask = AUX_CLK_PLL1_MASK,
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.scalable = 1,
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}, {
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.pclk = &pll3_48m_clk,
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.pclk_mask = AUX_CLK_PLL3_MASK,
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.scalable = 0,
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},
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};
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/* uart parent select structure */
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static struct pclk_sel uart_pclk_sel = {
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.pclk_info = uart_pclk_info,
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.pclk_count = ARRAY_SIZE(uart_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = UART_CLK_MASK,
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};
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/* uart clock */
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static struct clk uart_clk = {
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = UART_CLK_ENB,
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.pclk_sel = &uart_pclk_sel,
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.pclk_sel_shift = UART_CLK_SHIFT,
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.recalc = &aux_clk_recalc,
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.private_data = &uart_config,
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};
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/* firda configurations */
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static struct aux_clk_config firda_config = {
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.synth_reg = FIRDA_CLK_SYNT,
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};
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/* firda parents */
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static struct pclk_info firda_pclk_info[] = {
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{
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.pclk = &pll1_clk,
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.pclk_mask = AUX_CLK_PLL1_MASK,
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.scalable = 1,
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}, {
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.pclk = &pll3_48m_clk,
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.pclk_mask = AUX_CLK_PLL3_MASK,
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.scalable = 0,
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},
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};
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/* firda parent select structure */
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static struct pclk_sel firda_pclk_sel = {
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.pclk_info = firda_pclk_info,
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.pclk_count = ARRAY_SIZE(firda_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = FIRDA_CLK_MASK,
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};
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/* firda clock */
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static struct clk firda_clk = {
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = FIRDA_CLK_ENB,
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.pclk_sel = &firda_pclk_sel,
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.pclk_sel_shift = FIRDA_CLK_SHIFT,
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.recalc = &aux_clk_recalc,
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.private_data = &firda_config,
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};
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/* gpt parents */
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static struct pclk_info gpt_pclk_info[] = {
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{
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.pclk = &pll1_clk,
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.pclk_mask = AUX_CLK_PLL1_MASK,
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.scalable = 1,
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}, {
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.pclk = &pll3_48m_clk,
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.pclk_mask = AUX_CLK_PLL3_MASK,
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.scalable = 0,
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},
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};
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/* gpt parent select structure */
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static struct pclk_sel gpt_pclk_sel = {
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.pclk_info = gpt_pclk_info,
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.pclk_count = ARRAY_SIZE(gpt_pclk_info),
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.pclk_sel_reg = PERIP_CLK_CFG,
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.pclk_sel_mask = GPT_CLK_MASK,
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};
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/* gpt0 configurations */
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static struct aux_clk_config gpt0_config = {
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.synth_reg = PRSC1_CLK_CFG,
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};
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/* gpt0 timer clock */
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static struct clk gpt0_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk_sel = &gpt_pclk_sel,
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.pclk_sel_shift = GPT0_CLK_SHIFT,
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.recalc = &gpt_clk_recalc,
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.private_data = &gpt0_config,
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};
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/* gpt1 configurations */
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static struct aux_clk_config gpt1_config = {
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.synth_reg = PRSC2_CLK_CFG,
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};
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/* gpt1 timer clock */
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static struct clk gpt1_clk = {
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = GPT1_CLK_ENB,
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.pclk_sel = &gpt_pclk_sel,
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.pclk_sel_shift = GPT1_CLK_SHIFT,
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.recalc = &gpt_clk_recalc,
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.private_data = &gpt1_config,
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};
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/* gpt2 configurations */
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static struct aux_clk_config gpt2_config = {
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.synth_reg = PRSC3_CLK_CFG,
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};
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/* gpt2 timer clock */
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static struct clk gpt2_clk = {
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = GPT2_CLK_ENB,
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.pclk_sel = &gpt_pclk_sel,
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.pclk_sel_shift = GPT2_CLK_SHIFT,
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.recalc = &gpt_clk_recalc,
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.private_data = &gpt2_config,
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};
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/* clock derived from pll3 clk */
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/* usbh clock */
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static struct clk usbh_clk = {
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.pclk = &pll3_48m_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = USBH_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* usbd clock */
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static struct clk usbd_clk = {
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.pclk = &pll3_48m_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = USBD_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* clcd clock */
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static struct clk clcd_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &pll3_48m_clk,
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.recalc = &follow_parent,
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};
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/* clock derived from ahb clk */
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/* apb configuration structure */
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static struct bus_clk_config apb_config = {
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.reg = CORE_CLK_CFG,
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.mask = HCLK_PCLK_RATIO_MASK,
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.shift = HCLK_PCLK_RATIO_SHIFT,
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};
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/* apb clock */
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static struct clk apb_clk = {
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.flags = ALWAYS_ENABLED,
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.pclk = &ahb_clk,
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.recalc = &bus_clk_recalc,
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.private_data = &apb_config,
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};
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/* i2c clock */
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static struct clk i2c_clk = {
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.pclk = &ahb_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = I2C_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* dma clock */
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static struct clk dma_clk = {
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.pclk = &ahb_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = DMA_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* jpeg clock */
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static struct clk jpeg_clk = {
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.pclk = &ahb_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = JPEG_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* gmac clock */
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static struct clk gmac_clk = {
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.pclk = &ahb_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = GMAC_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* smi clock */
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static struct clk smi_clk = {
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.pclk = &ahb_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = SMI_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* c3 clock */
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static struct clk c3_clk = {
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.pclk = &ahb_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = C3_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* clock derived from apb clk */
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/* adc clock */
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static struct clk adc_clk = {
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.pclk = &apb_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = ADC_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* ssp clock */
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static struct clk ssp_clk = {
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.pclk = &apb_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = SSP_CLK_ENB,
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.recalc = &follow_parent,
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};
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/* gpio clock */
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static struct clk gpio_clk = {
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.pclk = &apb_clk,
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.en_reg = PERIP1_CLK_ENB,
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.en_reg_bit = GPIO_CLK_ENB,
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.recalc = &follow_parent,
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};
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static struct clk dummy_apb_pclk;
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/* array of all spear 3xx clock lookups */
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static struct clk_lookup spear_clk_lookups[] = {
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{ .con_id = "apb_pclk", .clk = &dummy_apb_pclk},
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/* root clks */
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{ .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
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{ .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
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/* clock derived from 32 KHz osc clk */
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{ .dev_id = "rtc", .clk = &rtc_clk},
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/* clock derived from 24 MHz osc clk */
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{ .con_id = "pll1_clk", .clk = &pll1_clk},
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{ .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
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{ .dev_id = "wdt", .clk = &wdt_clk},
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/* clock derived from pll1 clk */
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{ .con_id = "cpu_clk", .clk = &cpu_clk},
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{ .con_id = "ahb_clk", .clk = &ahb_clk},
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{ .dev_id = "uart", .clk = &uart_clk},
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{ .dev_id = "firda", .clk = &firda_clk},
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{ .dev_id = "gpt0", .clk = &gpt0_clk},
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{ .dev_id = "gpt1", .clk = &gpt1_clk},
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{ .dev_id = "gpt2", .clk = &gpt2_clk},
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/* clock derived from pll3 clk */
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{ .dev_id = "usbh", .clk = &usbh_clk},
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{ .dev_id = "usbd", .clk = &usbd_clk},
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{ .dev_id = "clcd", .clk = &clcd_clk},
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/* clock derived from ahb clk */
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{ .con_id = "apb_clk", .clk = &apb_clk},
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{ .dev_id = "i2c", .clk = &i2c_clk},
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{ .dev_id = "dma", .clk = &dma_clk},
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{ .dev_id = "jpeg", .clk = &jpeg_clk},
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{ .dev_id = "gmac", .clk = &gmac_clk},
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{ .dev_id = "smi", .clk = &smi_clk},
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{ .dev_id = "c3", .clk = &c3_clk},
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/* clock derived from apb clk */
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{ .dev_id = "adc", .clk = &adc_clk},
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{ .dev_id = "ssp", .clk = &ssp_clk},
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{ .dev_id = "gpio", .clk = &gpio_clk},
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};
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void __init clk_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
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clk_register(&spear_clk_lookups[i]);
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recalc_root_clocks();
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}
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