579 lines
14 KiB
C
579 lines
14 KiB
C
/*
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* arch/arm/kernel/kprobes-common.c
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*
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* Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
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*
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* Some contents moved here from arch/arm/include/asm/kprobes-arm.c which is
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* Copyright (C) 2006, 2007 Motorola Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/kprobes.h>
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#include <asm/system_info.h>
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#include "kprobes.h"
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#ifndef find_str_pc_offset
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/*
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* For STR and STM instructions, an ARM core may choose to use either
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* a +8 or a +12 displacement from the current instruction's address.
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* Whichever value is chosen for a given core, it must be the same for
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* both instructions and may not change. This function measures it.
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*/
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int str_pc_offset;
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void __init find_str_pc_offset(void)
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{
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int addr, scratch, ret;
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__asm__ (
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"sub %[ret], pc, #4 \n\t"
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"str pc, %[addr] \n\t"
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"ldr %[scr], %[addr] \n\t"
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"sub %[ret], %[scr], %[ret] \n\t"
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: [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
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str_pc_offset = ret;
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}
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#endif /* !find_str_pc_offset */
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#ifndef test_load_write_pc_interworking
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bool load_write_pc_interworks;
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void __init test_load_write_pc_interworking(void)
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{
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int arch = cpu_architecture();
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BUG_ON(arch == CPU_ARCH_UNKNOWN);
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load_write_pc_interworks = arch >= CPU_ARCH_ARMv5T;
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}
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#endif /* !test_load_write_pc_interworking */
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#ifndef test_alu_write_pc_interworking
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bool alu_write_pc_interworks;
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void __init test_alu_write_pc_interworking(void)
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{
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int arch = cpu_architecture();
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BUG_ON(arch == CPU_ARCH_UNKNOWN);
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alu_write_pc_interworks = arch >= CPU_ARCH_ARMv7;
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}
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#endif /* !test_alu_write_pc_interworking */
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void __init arm_kprobe_decode_init(void)
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{
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find_str_pc_offset();
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test_load_write_pc_interworking();
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test_alu_write_pc_interworking();
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}
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static unsigned long __kprobes __check_eq(unsigned long cpsr)
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{
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return cpsr & PSR_Z_BIT;
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}
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static unsigned long __kprobes __check_ne(unsigned long cpsr)
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{
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return (~cpsr) & PSR_Z_BIT;
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}
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static unsigned long __kprobes __check_cs(unsigned long cpsr)
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{
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return cpsr & PSR_C_BIT;
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}
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static unsigned long __kprobes __check_cc(unsigned long cpsr)
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{
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return (~cpsr) & PSR_C_BIT;
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}
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static unsigned long __kprobes __check_mi(unsigned long cpsr)
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{
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return cpsr & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_pl(unsigned long cpsr)
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{
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return (~cpsr) & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_vs(unsigned long cpsr)
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{
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return cpsr & PSR_V_BIT;
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}
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static unsigned long __kprobes __check_vc(unsigned long cpsr)
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{
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return (~cpsr) & PSR_V_BIT;
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}
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static unsigned long __kprobes __check_hi(unsigned long cpsr)
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{
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cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
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return cpsr & PSR_C_BIT;
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}
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static unsigned long __kprobes __check_ls(unsigned long cpsr)
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{
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cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
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return (~cpsr) & PSR_C_BIT;
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}
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static unsigned long __kprobes __check_ge(unsigned long cpsr)
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{
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cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
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return (~cpsr) & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_lt(unsigned long cpsr)
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{
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cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
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return cpsr & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_gt(unsigned long cpsr)
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{
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unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
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temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
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return (~temp) & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_le(unsigned long cpsr)
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{
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unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
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temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
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return temp & PSR_N_BIT;
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}
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static unsigned long __kprobes __check_al(unsigned long cpsr)
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{
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return true;
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}
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kprobe_check_cc * const kprobe_condition_checks[16] = {
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&__check_eq, &__check_ne, &__check_cs, &__check_cc,
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&__check_mi, &__check_pl, &__check_vs, &__check_vc,
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&__check_hi, &__check_ls, &__check_ge, &__check_lt,
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&__check_gt, &__check_le, &__check_al, &__check_al
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};
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void __kprobes kprobe_simulate_nop(struct kprobe *p, struct pt_regs *regs)
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{
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}
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void __kprobes kprobe_emulate_none(struct kprobe *p, struct pt_regs *regs)
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{
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p->ainsn.insn_fn();
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}
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static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
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{
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kprobe_opcode_t insn = p->opcode;
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int rn = (insn >> 16) & 0xf;
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int lbit = insn & (1 << 20);
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int wbit = insn & (1 << 21);
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int ubit = insn & (1 << 23);
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int pbit = insn & (1 << 24);
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long *addr = (long *)regs->uregs[rn];
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int reg_bit_vector;
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int reg_count;
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reg_count = 0;
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reg_bit_vector = insn & 0xffff;
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while (reg_bit_vector) {
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reg_bit_vector &= (reg_bit_vector - 1);
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++reg_count;
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}
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if (!ubit)
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addr -= reg_count;
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addr += (!pbit == !ubit);
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reg_bit_vector = insn & 0xffff;
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while (reg_bit_vector) {
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int reg = __ffs(reg_bit_vector);
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reg_bit_vector &= (reg_bit_vector - 1);
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if (lbit)
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regs->uregs[reg] = *addr++;
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else
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*addr++ = regs->uregs[reg];
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}
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if (wbit) {
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if (!ubit)
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addr -= reg_count;
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addr -= (!pbit == !ubit);
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regs->uregs[rn] = (long)addr;
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}
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}
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static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs)
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{
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regs->ARM_pc = (long)p->addr + str_pc_offset;
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simulate_ldm1stm1(p, regs);
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regs->ARM_pc = (long)p->addr + 4;
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}
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static void __kprobes simulate_ldm1_pc(struct kprobe *p, struct pt_regs *regs)
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{
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simulate_ldm1stm1(p, regs);
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load_write_pc(regs->ARM_pc, regs);
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}
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static void __kprobes
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emulate_generic_r0_12_noflags(struct kprobe *p, struct pt_regs *regs)
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{
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register void *rregs asm("r1") = regs;
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register void *rfn asm("lr") = p->ainsn.insn_fn;
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__asm__ __volatile__ (
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"stmdb sp!, {%[regs], r11} \n\t"
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"ldmia %[regs], {r0-r12} \n\t"
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#if __LINUX_ARM_ARCH__ >= 6
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"blx %[fn] \n\t"
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#else
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"str %[fn], [sp, #-4]! \n\t"
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"adr lr, 1f \n\t"
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"ldr pc, [sp], #4 \n\t"
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"1: \n\t"
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#endif
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"ldr lr, [sp], #4 \n\t" /* lr = regs */
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"stmia lr, {r0-r12} \n\t"
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"ldr r11, [sp], #4 \n\t"
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: [regs] "=r" (rregs), [fn] "=r" (rfn)
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: "0" (rregs), "1" (rfn)
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: "r0", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r12", "memory", "cc"
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);
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}
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static void __kprobes
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emulate_generic_r2_14_noflags(struct kprobe *p, struct pt_regs *regs)
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{
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emulate_generic_r0_12_noflags(p, (struct pt_regs *)(regs->uregs+2));
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}
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static void __kprobes
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emulate_ldm_r3_15(struct kprobe *p, struct pt_regs *regs)
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{
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emulate_generic_r0_12_noflags(p, (struct pt_regs *)(regs->uregs+3));
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load_write_pc(regs->ARM_pc, regs);
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}
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enum kprobe_insn __kprobes
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kprobe_decode_ldmstm(kprobe_opcode_t insn, struct arch_specific_insn *asi)
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{
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kprobe_insn_handler_t *handler = 0;
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unsigned reglist = insn & 0xffff;
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int is_ldm = insn & 0x100000;
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int rn = (insn >> 16) & 0xf;
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if (rn <= 12 && (reglist & 0xe000) == 0) {
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/* Instruction only uses registers in the range R0..R12 */
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handler = emulate_generic_r0_12_noflags;
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} else if (rn >= 2 && (reglist & 0x8003) == 0) {
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/* Instruction only uses registers in the range R2..R14 */
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rn -= 2;
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reglist >>= 2;
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handler = emulate_generic_r2_14_noflags;
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} else if (rn >= 3 && (reglist & 0x0007) == 0) {
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/* Instruction only uses registers in the range R3..R15 */
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if (is_ldm && (reglist & 0x8000)) {
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rn -= 3;
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reglist >>= 3;
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handler = emulate_ldm_r3_15;
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}
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}
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if (handler) {
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/* We can emulate the instruction in (possibly) modified form */
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asi->insn[0] = (insn & 0xfff00000) | (rn << 16) | reglist;
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asi->insn_handler = handler;
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return INSN_GOOD;
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}
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/* Fallback to slower simulation... */
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if (reglist & 0x8000)
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handler = is_ldm ? simulate_ldm1_pc : simulate_stm1_pc;
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else
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handler = simulate_ldm1stm1;
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asi->insn_handler = handler;
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return INSN_GOOD_NO_SLOT;
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}
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/*
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* Prepare an instruction slot to receive an instruction for emulating.
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* This is done by placing a subroutine return after the location where the
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* instruction will be placed. We also modify ARM instructions to be
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* unconditional as the condition code will already be checked before any
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* emulation handler is called.
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*/
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static kprobe_opcode_t __kprobes
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prepare_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
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bool thumb)
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{
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#ifdef CONFIG_THUMB2_KERNEL
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if (thumb) {
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u16 *thumb_insn = (u16 *)asi->insn;
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thumb_insn[1] = 0x4770; /* Thumb bx lr */
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thumb_insn[2] = 0x4770; /* Thumb bx lr */
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return insn;
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}
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asi->insn[1] = 0xe12fff1e; /* ARM bx lr */
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#else
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asi->insn[1] = 0xe1a0f00e; /* mov pc, lr */
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#endif
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/* Make an ARM instruction unconditional */
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if (insn < 0xe0000000)
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insn = (insn | 0xe0000000) & ~0x10000000;
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return insn;
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}
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/*
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* Write a (probably modified) instruction into the slot previously prepared by
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* prepare_emulated_insn
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*/
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static void __kprobes
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set_emulated_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
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bool thumb)
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{
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#ifdef CONFIG_THUMB2_KERNEL
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if (thumb) {
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u16 *ip = (u16 *)asi->insn;
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if (is_wide_instruction(insn))
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*ip++ = insn >> 16;
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*ip++ = insn;
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return;
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}
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#endif
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asi->insn[0] = insn;
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}
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/*
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* When we modify the register numbers encoded in an instruction to be emulated,
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* the new values come from this define. For ARM and 32-bit Thumb instructions
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* this gives...
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*
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* bit position 16 12 8 4 0
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* ---------------+---+---+---+---+---+
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* register r2 r0 r1 -- r3
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*/
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#define INSN_NEW_BITS 0x00020103
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/* Each nibble has same value as that at INSN_NEW_BITS bit 16 */
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#define INSN_SAMEAS16_BITS 0x22222222
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/*
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* Validate and modify each of the registers encoded in an instruction.
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*
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* Each nibble in regs contains a value from enum decode_reg_type. For each
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* non-zero value, the corresponding nibble in pinsn is validated and modified
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* according to the type.
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*/
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static bool __kprobes decode_regs(kprobe_opcode_t* pinsn, u32 regs)
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{
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kprobe_opcode_t insn = *pinsn;
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kprobe_opcode_t mask = 0xf; /* Start at least significant nibble */
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for (; regs != 0; regs >>= 4, mask <<= 4) {
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kprobe_opcode_t new_bits = INSN_NEW_BITS;
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switch (regs & 0xf) {
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case REG_TYPE_NONE:
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/* Nibble not a register, skip to next */
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continue;
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case REG_TYPE_ANY:
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/* Any register is allowed */
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break;
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case REG_TYPE_SAMEAS16:
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/* Replace register with same as at bit position 16 */
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new_bits = INSN_SAMEAS16_BITS;
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break;
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case REG_TYPE_SP:
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/* Only allow SP (R13) */
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if ((insn ^ 0xdddddddd) & mask)
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goto reject;
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break;
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case REG_TYPE_PC:
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/* Only allow PC (R15) */
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if ((insn ^ 0xffffffff) & mask)
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goto reject;
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break;
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case REG_TYPE_NOSP:
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/* Reject SP (R13) */
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if (((insn ^ 0xdddddddd) & mask) == 0)
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goto reject;
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break;
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case REG_TYPE_NOSPPC:
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case REG_TYPE_NOSPPCX:
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/* Reject SP and PC (R13 and R15) */
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if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0)
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goto reject;
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break;
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case REG_TYPE_NOPCWB:
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if (!is_writeback(insn))
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break; /* No writeback, so any register is OK */
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/* fall through... */
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case REG_TYPE_NOPC:
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case REG_TYPE_NOPCX:
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/* Reject PC (R15) */
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if (((insn ^ 0xffffffff) & mask) == 0)
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goto reject;
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break;
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}
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/* Replace value of nibble with new register number... */
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insn &= ~mask;
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insn |= new_bits & mask;
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}
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*pinsn = insn;
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return true;
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reject:
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return false;
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}
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|
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static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
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[DECODE_TYPE_TABLE] = sizeof(struct decode_table),
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[DECODE_TYPE_CUSTOM] = sizeof(struct decode_custom),
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[DECODE_TYPE_SIMULATE] = sizeof(struct decode_simulate),
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[DECODE_TYPE_EMULATE] = sizeof(struct decode_emulate),
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[DECODE_TYPE_OR] = sizeof(struct decode_or),
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[DECODE_TYPE_REJECT] = sizeof(struct decode_reject)
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};
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|
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/*
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* kprobe_decode_insn operates on data tables in order to decode an ARM
|
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* architecture instruction onto which a kprobe has been placed.
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*
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* These instruction decoding tables are a concatenation of entries each
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* of which consist of one of the following structs:
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*
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* decode_table
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* decode_custom
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* decode_simulate
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* decode_emulate
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* decode_or
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* decode_reject
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*
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* Each of these starts with a struct decode_header which has the following
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* fields:
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*
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* type_regs
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* mask
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* value
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*
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* The least significant DECODE_TYPE_BITS of type_regs contains a value
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* from enum decode_type, this indicates which of the decode_* structs
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* the entry contains. The value DECODE_TYPE_END indicates the end of the
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* table.
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*
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* When the table is parsed, each entry is checked in turn to see if it
|
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* matches the instruction to be decoded using the test:
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*
|
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* (insn & mask) == value
|
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*
|
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* If no match is found before the end of the table is reached then decoding
|
|
* fails with INSN_REJECTED.
|
|
*
|
|
* When a match is found, decode_regs() is called to validate and modify each
|
|
* of the registers encoded in the instruction; the data it uses to do this
|
|
* is (type_regs >> DECODE_TYPE_BITS). A validation failure will cause decoding
|
|
* to fail with INSN_REJECTED.
|
|
*
|
|
* Once the instruction has passed the above tests, further processing
|
|
* depends on the type of the table entry's decode struct.
|
|
*
|
|
*/
|
|
int __kprobes
|
|
kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
|
|
const union decode_item *table, bool thumb)
|
|
{
|
|
const struct decode_header *h = (struct decode_header *)table;
|
|
const struct decode_header *next;
|
|
bool matched = false;
|
|
|
|
insn = prepare_emulated_insn(insn, asi, thumb);
|
|
|
|
for (;; h = next) {
|
|
enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
|
|
u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
|
|
|
|
if (type == DECODE_TYPE_END)
|
|
return INSN_REJECTED;
|
|
|
|
next = (struct decode_header *)
|
|
((uintptr_t)h + decode_struct_sizes[type]);
|
|
|
|
if (!matched && (insn & h->mask.bits) != h->value.bits)
|
|
continue;
|
|
|
|
if (!decode_regs(&insn, regs))
|
|
return INSN_REJECTED;
|
|
|
|
switch (type) {
|
|
|
|
case DECODE_TYPE_TABLE: {
|
|
struct decode_table *d = (struct decode_table *)h;
|
|
next = (struct decode_header *)d->table.table;
|
|
break;
|
|
}
|
|
|
|
case DECODE_TYPE_CUSTOM: {
|
|
struct decode_custom *d = (struct decode_custom *)h;
|
|
return (*d->decoder.decoder)(insn, asi);
|
|
}
|
|
|
|
case DECODE_TYPE_SIMULATE: {
|
|
struct decode_simulate *d = (struct decode_simulate *)h;
|
|
asi->insn_handler = d->handler.handler;
|
|
return INSN_GOOD_NO_SLOT;
|
|
}
|
|
|
|
case DECODE_TYPE_EMULATE: {
|
|
struct decode_emulate *d = (struct decode_emulate *)h;
|
|
asi->insn_handler = d->handler.handler;
|
|
set_emulated_insn(insn, asi, thumb);
|
|
return INSN_GOOD;
|
|
}
|
|
|
|
case DECODE_TYPE_OR:
|
|
matched = true;
|
|
break;
|
|
|
|
case DECODE_TYPE_REJECT:
|
|
default:
|
|
return INSN_REJECTED;
|
|
}
|
|
}
|
|
}
|