195 lines
5.3 KiB
C
195 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* AD9523 SPI Low Jitter Clock Generator
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*
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* Copyright 2012 Analog Devices Inc.
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*/
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#ifndef IIO_FREQUENCY_AD9523_H_
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#define IIO_FREQUENCY_AD9523_H_
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enum outp_drv_mode {
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TRISTATE,
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LVPECL_8mA,
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LVDS_4mA,
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LVDS_7mA,
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HSTL0_16mA,
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HSTL1_8mA,
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CMOS_CONF1,
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CMOS_CONF2,
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CMOS_CONF3,
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CMOS_CONF4,
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CMOS_CONF5,
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CMOS_CONF6,
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CMOS_CONF7,
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CMOS_CONF8,
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CMOS_CONF9
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};
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enum ref_sel_mode {
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NONEREVERTIVE_STAY_ON_REFB,
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REVERT_TO_REFA,
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SELECT_REFA,
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SELECT_REFB,
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EXT_REF_SEL
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};
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/**
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* struct ad9523_channel_spec - Output channel configuration
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*
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* @channel_num: Output channel number.
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* @divider_output_invert_en: Invert the polarity of the output clock.
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* @sync_ignore_en: Ignore chip-level SYNC signal.
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* @low_power_mode_en: Reduce power used in the differential output modes.
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* @use_alt_clock_src: Channel divider uses alternative clk source.
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* @output_dis: Disables, powers down the entire channel.
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* @driver_mode: Output driver mode (logic level family).
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* @divider_phase: Divider initial phase after a SYNC. Range 0..63
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LSB = 1/2 of a period of the divider input clock.
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* @channel_divider: 10-bit channel divider.
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* @extended_name: Optional descriptive channel name.
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*/
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struct ad9523_channel_spec {
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unsigned channel_num;
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bool divider_output_invert_en;
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bool sync_ignore_en;
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bool low_power_mode_en;
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/* CH0..CH3 VCXO, CH4..CH9 VCO2 */
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bool use_alt_clock_src;
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bool output_dis;
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enum outp_drv_mode driver_mode;
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unsigned char divider_phase;
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unsigned short channel_divider;
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char extended_name[16];
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};
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enum pll1_rzero_resistor {
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RZERO_883_OHM,
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RZERO_677_OHM,
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RZERO_341_OHM,
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RZERO_135_OHM,
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RZERO_10_OHM,
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RZERO_USE_EXT_RES = 8,
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};
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enum rpole2_resistor {
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RPOLE2_900_OHM,
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RPOLE2_450_OHM,
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RPOLE2_300_OHM,
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RPOLE2_225_OHM,
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};
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enum rzero_resistor {
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RZERO_3250_OHM,
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RZERO_2750_OHM,
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RZERO_2250_OHM,
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RZERO_2100_OHM,
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RZERO_3000_OHM,
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RZERO_2500_OHM,
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RZERO_2000_OHM,
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RZERO_1850_OHM,
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};
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enum cpole1_capacitor {
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CPOLE1_0_PF,
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CPOLE1_8_PF,
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CPOLE1_16_PF,
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CPOLE1_24_PF,
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_CPOLE1_24_PF, /* place holder */
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CPOLE1_32_PF,
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CPOLE1_40_PF,
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CPOLE1_48_PF,
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};
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/**
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* struct ad9523_platform_data - platform specific information
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*
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* @vcxo_freq: External VCXO frequency in Hz
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* @refa_diff_rcv_en: REFA differential/single-ended input selection.
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* @refb_diff_rcv_en: REFB differential/single-ended input selection.
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* @zd_in_diff_en: Zero Delay differential/single-ended input selection.
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* @osc_in_diff_en: OSC differential/ single-ended input selection.
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* @refa_cmos_neg_inp_en: REFA single-ended neg./pos. input enable.
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* @refb_cmos_neg_inp_en: REFB single-ended neg./pos. input enable.
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* @zd_in_cmos_neg_inp_en: Zero Delay single-ended neg./pos. input enable.
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* @osc_in_cmos_neg_inp_en: OSC single-ended neg./pos. input enable.
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* @refa_r_div: PLL1 10-bit REFA R divider.
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* @refb_r_div: PLL1 10-bit REFB R divider.
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* @pll1_feedback_div: PLL1 10-bit Feedback N divider.
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* @pll1_charge_pump_current_nA: Magnitude of PLL1 charge pump current (nA).
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* @zero_delay_mode_internal_en: Internal, external Zero Delay mode selection.
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* @osc_in_feedback_en: PLL1 feedback path, local feedback from
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* the OSC_IN receiver or zero delay mode
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* @pll1_loop_filter_rzero: PLL1 Loop Filter Zero Resistor selection.
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* @ref_mode: Reference selection mode.
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* @pll2_charge_pump_current_nA: Magnitude of PLL2 charge pump current (nA).
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* @pll2_ndiv_a_cnt: PLL2 Feedback N-divider, A Counter, range 0..4.
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* @pll2_ndiv_b_cnt: PLL2 Feedback N-divider, B Counter, range 0..63.
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* @pll2_freq_doubler_en: PLL2 frequency doubler enable.
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* @pll2_r2_div: PLL2 R2 divider, range 0..31.
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* @pll2_vco_div_m1: VCO1 divider, range 3..5.
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* @pll2_vco_div_m2: VCO2 divider, range 3..5.
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* @rpole2: PLL2 loop filter Rpole resistor value.
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* @rzero: PLL2 loop filter Rzero resistor value.
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* @cpole1: PLL2 loop filter Cpole capacitor value.
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* @rzero_bypass_en: PLL2 loop filter Rzero bypass enable.
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* @num_channels: Array size of struct ad9523_channel_spec.
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* @channels: Pointer to channel array.
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* @name: Optional alternative iio device name.
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*/
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struct ad9523_platform_data {
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unsigned long vcxo_freq;
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/* Differential/ Single-Ended Input Configuration */
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bool refa_diff_rcv_en;
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bool refb_diff_rcv_en;
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bool zd_in_diff_en;
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bool osc_in_diff_en;
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/*
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* Valid if differential input disabled
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* if false defaults to pos input
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*/
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bool refa_cmos_neg_inp_en;
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bool refb_cmos_neg_inp_en;
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bool zd_in_cmos_neg_inp_en;
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bool osc_in_cmos_neg_inp_en;
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/* PLL1 Setting */
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unsigned short refa_r_div;
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unsigned short refb_r_div;
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unsigned short pll1_feedback_div;
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unsigned short pll1_charge_pump_current_nA;
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bool zero_delay_mode_internal_en;
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bool osc_in_feedback_en;
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enum pll1_rzero_resistor pll1_loop_filter_rzero;
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/* Reference */
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enum ref_sel_mode ref_mode;
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/* PLL2 Setting */
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unsigned int pll2_charge_pump_current_nA;
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unsigned char pll2_ndiv_a_cnt;
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unsigned char pll2_ndiv_b_cnt;
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bool pll2_freq_doubler_en;
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unsigned char pll2_r2_div;
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unsigned char pll2_vco_div_m1; /* 3..5 */
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unsigned char pll2_vco_div_m2; /* 3..5 */
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/* Loop Filter PLL2 */
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enum rpole2_resistor rpole2;
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enum rzero_resistor rzero;
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enum cpole1_capacitor cpole1;
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bool rzero_bypass_en;
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/* Output Channel Configuration */
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int num_channels;
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struct ad9523_channel_spec *channels;
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char name[SPI_NAME_SIZE];
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};
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#endif /* IIO_FREQUENCY_AD9523_H_ */
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