342 lines
12 KiB
C
342 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2017 MediaTek Inc.
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// Author: Chenglin Xu <chenglin.xu@mediatek.com>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/mt6380-regulator.h>
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#include <linux/regulator/of_regulator.h>
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/* PMIC Registers */
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#define MT6380_ALDO_CON_0 0x0000
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#define MT6380_BTLDO_CON_0 0x0004
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#define MT6380_COMP_CON_0 0x0008
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#define MT6380_CPUBUCK_CON_0 0x000C
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#define MT6380_CPUBUCK_CON_1 0x0010
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#define MT6380_CPUBUCK_CON_2 0x0014
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#define MT6380_DDRLDO_CON_0 0x0018
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#define MT6380_MLDO_CON_0 0x001C
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#define MT6380_PALDO_CON_0 0x0020
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#define MT6380_PHYLDO_CON_0 0x0024
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#define MT6380_SIDO_CON_0 0x0028
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#define MT6380_SIDO_CON_1 0x002C
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#define MT6380_SIDO_CON_2 0x0030
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#define MT6380_SLDO_CON_0 0x0034
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#define MT6380_TLDO_CON_0 0x0038
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#define MT6380_STARTUP_CON_0 0x003C
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#define MT6380_STARTUP_CON_1 0x0040
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#define MT6380_SMPS_TOP_CON_0 0x0044
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#define MT6380_SMPS_TOP_CON_1 0x0048
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#define MT6380_ANA_CTRL_0 0x0050
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#define MT6380_ANA_CTRL_1 0x0054
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#define MT6380_ANA_CTRL_2 0x0058
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#define MT6380_ANA_CTRL_3 0x005C
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#define MT6380_ANA_CTRL_4 0x0060
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#define MT6380_SPK_CON9 0x0064
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#define MT6380_SPK_CON11 0x0068
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#define MT6380_SPK_CON12 0x006A
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#define MT6380_CLK_CTRL 0x0070
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#define MT6380_PINMUX_CTRL 0x0074
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#define MT6380_IO_CTRL 0x0078
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#define MT6380_SLP_MODE_CTRL_0 0x007C
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#define MT6380_SLP_MODE_CTRL_1 0x0080
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#define MT6380_SLP_MODE_CTRL_2 0x0084
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#define MT6380_SLP_MODE_CTRL_3 0x0088
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#define MT6380_SLP_MODE_CTRL_4 0x008C
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#define MT6380_SLP_MODE_CTRL_5 0x0090
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#define MT6380_SLP_MODE_CTRL_6 0x0094
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#define MT6380_SLP_MODE_CTRL_7 0x0098
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#define MT6380_SLP_MODE_CTRL_8 0x009C
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#define MT6380_FCAL_CTRL_0 0x00A0
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#define MT6380_FCAL_CTRL_1 0x00A4
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#define MT6380_LDO_CTRL_0 0x00A8
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#define MT6380_LDO_CTRL_1 0x00AC
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#define MT6380_LDO_CTRL_2 0x00B0
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#define MT6380_LDO_CTRL_3 0x00B4
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#define MT6380_LDO_CTRL_4 0x00B8
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#define MT6380_DEBUG_CTRL_0 0x00BC
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#define MT6380_EFU_CTRL_0 0x0200
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#define MT6380_EFU_CTRL_1 0x0201
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#define MT6380_EFU_CTRL_2 0x0202
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#define MT6380_EFU_CTRL_3 0x0203
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#define MT6380_EFU_CTRL_4 0x0204
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#define MT6380_EFU_CTRL_5 0x0205
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#define MT6380_EFU_CTRL_6 0x0206
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#define MT6380_EFU_CTRL_7 0x0207
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#define MT6380_EFU_CTRL_8 0x0208
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#define MT6380_REGULATOR_MODE_AUTO 0
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#define MT6380_REGULATOR_MODE_FORCE_PWM 1
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/*
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* mt6380 regulators' information
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*
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* @desc: standard fields of regulator description
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* @vselon_reg: Register sections for hardware control mode of bucks
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* @modeset_reg: Register for controlling the buck/LDO control mode
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* @modeset_mask: Mask for controlling the buck/LDO control mode
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*/
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struct mt6380_regulator_info {
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struct regulator_desc desc;
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u32 vselon_reg;
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u32 modeset_reg;
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u32 modeset_mask;
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};
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#define MT6380_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
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vosel, vosel_mask, enbit, voselon, _modeset_reg, \
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_modeset_mask) \
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[MT6380_ID_##vreg] = { \
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.desc = { \
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.name = #vreg, \
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.of_match = of_match_ptr(match), \
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.ops = &mt6380_volt_range_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = MT6380_ID_##vreg, \
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.owner = THIS_MODULE, \
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.n_voltages = ((max) - (min)) / (step) + 1, \
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.linear_ranges = volt_ranges, \
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.n_linear_ranges = ARRAY_SIZE(volt_ranges), \
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.vsel_reg = vosel, \
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.vsel_mask = vosel_mask, \
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.enable_reg = enreg, \
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.enable_mask = BIT(enbit), \
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}, \
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.vselon_reg = voselon, \
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.modeset_reg = _modeset_reg, \
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.modeset_mask = _modeset_mask, \
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}
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#define MT6380_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
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vosel_mask, _modeset_reg, _modeset_mask) \
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[MT6380_ID_##vreg] = { \
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.desc = { \
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.name = #vreg, \
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.of_match = of_match_ptr(match), \
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.ops = &mt6380_volt_table_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = MT6380_ID_##vreg, \
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.owner = THIS_MODULE, \
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.n_voltages = ARRAY_SIZE(ldo_volt_table), \
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.volt_table = ldo_volt_table, \
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.vsel_reg = vosel, \
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.vsel_mask = vosel_mask, \
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.enable_reg = enreg, \
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.enable_mask = BIT(enbit), \
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}, \
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.modeset_reg = _modeset_reg, \
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.modeset_mask = _modeset_mask, \
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}
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#define MT6380_REG_FIXED(match, vreg, enreg, enbit, volt, \
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_modeset_reg, _modeset_mask) \
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[MT6380_ID_##vreg] = { \
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.desc = { \
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.name = #vreg, \
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.of_match = of_match_ptr(match), \
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.ops = &mt6380_volt_fixed_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = MT6380_ID_##vreg, \
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.owner = THIS_MODULE, \
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.n_voltages = 1, \
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.enable_reg = enreg, \
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.enable_mask = BIT(enbit), \
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.min_uV = volt, \
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}, \
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.modeset_reg = _modeset_reg, \
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.modeset_mask = _modeset_mask, \
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}
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static const struct linear_range buck_volt_range1[] = {
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REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250),
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};
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static const struct linear_range buck_volt_range2[] = {
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REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250),
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};
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static const struct linear_range buck_volt_range3[] = {
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REGULATOR_LINEAR_RANGE(1200000, 0, 0x3c, 25000),
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};
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static const unsigned int ldo_volt_table1[] = {
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1400000, 1350000, 1300000, 1250000, 1200000, 1150000, 1100000, 1050000,
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};
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static const unsigned int ldo_volt_table2[] = {
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2200000, 3300000,
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};
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static const unsigned int ldo_volt_table3[] = {
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1240000, 1390000, 1540000, 1840000,
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};
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static const unsigned int ldo_volt_table4[] = {
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2200000, 3300000,
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};
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static int mt6380_regulator_set_mode(struct regulator_dev *rdev,
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unsigned int mode)
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{
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int val = 0;
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struct mt6380_regulator_info *info = rdev_get_drvdata(rdev);
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switch (mode) {
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case REGULATOR_MODE_NORMAL:
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val = MT6380_REGULATOR_MODE_AUTO;
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break;
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case REGULATOR_MODE_FAST:
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val = MT6380_REGULATOR_MODE_FORCE_PWM;
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break;
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default:
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return -EINVAL;
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}
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val <<= ffs(info->modeset_mask) - 1;
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return regmap_update_bits(rdev->regmap, info->modeset_reg,
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info->modeset_mask, val);
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}
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static unsigned int mt6380_regulator_get_mode(struct regulator_dev *rdev)
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{
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unsigned int val;
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unsigned int mode;
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int ret;
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struct mt6380_regulator_info *info = rdev_get_drvdata(rdev);
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ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
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if (ret < 0)
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return ret;
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val &= info->modeset_mask;
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val >>= ffs(info->modeset_mask) - 1;
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switch (val) {
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case MT6380_REGULATOR_MODE_AUTO:
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mode = REGULATOR_MODE_NORMAL;
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break;
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case MT6380_REGULATOR_MODE_FORCE_PWM:
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mode = REGULATOR_MODE_FAST;
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break;
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default:
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return -EINVAL;
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}
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return mode;
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}
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static const struct regulator_ops mt6380_volt_range_ops = {
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.list_voltage = regulator_list_voltage_linear_range,
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.map_voltage = regulator_map_voltage_linear_range,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.set_voltage_time_sel = regulator_set_voltage_time_sel,
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.set_mode = mt6380_regulator_set_mode,
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.get_mode = mt6380_regulator_get_mode,
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};
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static const struct regulator_ops mt6380_volt_table_ops = {
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.list_voltage = regulator_list_voltage_table,
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.map_voltage = regulator_map_voltage_iterate,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.set_voltage_time_sel = regulator_set_voltage_time_sel,
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.set_mode = mt6380_regulator_set_mode,
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.get_mode = mt6380_regulator_get_mode,
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};
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static const struct regulator_ops mt6380_volt_fixed_ops = {
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.list_voltage = regulator_list_voltage_linear,
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.set_mode = mt6380_regulator_set_mode,
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.get_mode = mt6380_regulator_get_mode,
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};
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/* The array is indexed by id(MT6380_ID_XXX) */
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static struct mt6380_regulator_info mt6380_regulators[] = {
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MT6380_BUCK("buck-vcore1", VCPU, 600000, 1393750, 6250,
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buck_volt_range1, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_1,
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0xfe, 3, MT6380_ANA_CTRL_1,
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MT6380_CPUBUCK_CON_0, 0x8000000),
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MT6380_BUCK("buck-vcore", VCORE, 600000, 1393750, 6250,
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buck_volt_range2, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_2,
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0xfe, 2, MT6380_ANA_CTRL_2, MT6380_SIDO_CON_0, 0x1000000),
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MT6380_BUCK("buck-vrf", VRF, 1200000, 1575000, 25000,
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buck_volt_range3, MT6380_ANA_CTRL_3, MT6380_SIDO_CON_0,
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0x78, 1, MT6380_SIDO_CON_0, MT6380_SIDO_CON_0, 0x8000),
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MT6380_LDO("ldo-vm", VMLDO, ldo_volt_table1, MT6380_LDO_CTRL_0,
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1, MT6380_MLDO_CON_0, 0xE000, MT6380_ANA_CTRL_1, 0x4000000),
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MT6380_LDO("ldo-va", VALDO, ldo_volt_table2, MT6380_LDO_CTRL_0,
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2, MT6380_ALDO_CON_0, 0x400, MT6380_ALDO_CON_0, 0x20),
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MT6380_REG_FIXED("ldo-vphy", VPHYLDO, MT6380_LDO_CTRL_0, 7, 1800000,
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MT6380_PHYLDO_CON_0, 0x80),
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MT6380_LDO("ldo-vddr", VDDRLDO, ldo_volt_table3, MT6380_LDO_CTRL_0,
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8, MT6380_DDRLDO_CON_0, 0x3000, MT6380_DDRLDO_CON_0, 0x80),
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MT6380_LDO("ldo-vt", VTLDO, ldo_volt_table4, MT6380_LDO_CTRL_0, 3,
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MT6380_TLDO_CON_0, 0x400, MT6380_TLDO_CON_0, 0x20),
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};
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static int mt6380_regulator_probe(struct platform_device *pdev)
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{
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struct regmap *regmap = dev_get_regmap(pdev->dev.parent, NULL);
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struct regulator_config config = {};
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struct regulator_dev *rdev;
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int i;
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for (i = 0; i < MT6380_MAX_REGULATOR; i++) {
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config.dev = &pdev->dev;
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config.driver_data = &mt6380_regulators[i];
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config.regmap = regmap;
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rdev = devm_regulator_register(&pdev->dev,
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&mt6380_regulators[i].desc,
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&config);
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if (IS_ERR(rdev)) {
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dev_err(&pdev->dev, "failed to register %s\n",
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mt6380_regulators[i].desc.name);
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return PTR_ERR(rdev);
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}
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}
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return 0;
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}
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static const struct platform_device_id mt6380_platform_ids[] = {
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{"mt6380-regulator", 0},
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(platform, mt6380_platform_ids);
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static const struct of_device_id __maybe_unused mt6380_of_match[] = {
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{ .compatible = "mediatek,mt6380-regulator", },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, mt6380_of_match);
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static struct platform_driver mt6380_regulator_driver = {
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.driver = {
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.name = "mt6380-regulator",
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.of_match_table = of_match_ptr(mt6380_of_match),
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},
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.probe = mt6380_regulator_probe,
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.id_table = mt6380_platform_ids,
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};
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module_platform_driver(mt6380_regulator_driver);
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MODULE_AUTHOR("Chenglin Xu <chenglin.xu@mediatek.com>");
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MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6380 PMIC");
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MODULE_LICENSE("GPL v2");
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