156 lines
4.3 KiB
YAML
156 lines
4.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek MT8192 Pin Controller
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maintainers:
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- Sean Wang <sean.wang@mediatek.com>
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description: |
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The Mediatek's Pin controller is used to control SoC pins.
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properties:
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compatible:
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const: mediatek,mt8192-pinctrl
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gpio-controller: true
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'#gpio-cells':
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description: |
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Number of cells in GPIO specifier. Since the generic GPIO binding is used,
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the amount of cells must be specified as 2. See the below
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mentioned gpio binding representation for description of particular cells.
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const: 2
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gpio-ranges:
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description: gpio valid number range.
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maxItems: 1
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reg:
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description: |
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Physical address base for gpio base registers. There are 11 GPIO
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physical address base in mt8192.
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maxItems: 11
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reg-names:
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description: |
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Gpio base register names.
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maxItems: 11
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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interrupts:
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description: The interrupt outputs to sysirq.
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maxItems: 1
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#PIN CONFIGURATION NODES
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patternProperties:
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'^pins':
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type: object
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description: |
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A pinctrl node should contain at least one subnodes representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, pullups, drive strength, input enable/disable and
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input schmitt.
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An example of using macro:
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pincontroller {
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/* GPIO0 set as multifunction GPIO0 */
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state_0_node_a {
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pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
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};
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/* GPIO1 set as multifunction PWM */
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state_0_node_b {
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pinmux = <PINMUX_GPIO1__FUNC_PWM_1>;
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};
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};
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$ref: "pinmux-node.yaml"
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properties:
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pinmux:
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description: |
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Integer array, represents gpio pin number and mux setting.
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Supported pin number and mux varies for different SoCs, and are defined
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as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
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drive-strength:
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description: |
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It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
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dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
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enum: [2, 4, 6, 8, 10, 12, 14, 16]
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bias-pull-down: true
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bias-pull-up: true
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bias-disable: true
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output-high: true
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output-low: true
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input-enable: true
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input-disable: true
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input-schmitt-enable: true
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input-schmitt-disable: true
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required:
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- pinmux
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt8192-pinctrl";
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reg = <0x10005000 0x1000>,
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<0x11c20000 0x1000>,
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<0x11d10000 0x1000>,
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<0x11d30000 0x1000>,
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<0x11d40000 0x1000>,
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<0x11e20000 0x1000>,
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<0x11e70000 0x1000>,
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<0x11ea0000 0x1000>,
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<0x11f20000 0x1000>,
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<0x11f30000 0x1000>,
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<0x1000b000 0x1000>;
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reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
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"iocfg_bl", "iocfg_br", "iocfg_lm",
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"iocfg_lb", "iocfg_rt", "iocfg_lt",
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"iocfg_tl", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 220>;
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interrupt-controller;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
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#interrupt-cells = <2>;
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pins {
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pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
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output-low;
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};
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};
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