147 lines
3.9 KiB
YAML
147 lines
3.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MIPS Global Interrupt Controller
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maintainers:
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- Paul Burton <paulburton@kernel.org>
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- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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description: |
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The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
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It also supports local (per-processor) interrupts and software-generated
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interrupts which can be used as IPIs. The GIC also includes a free-running
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global timer, per-CPU count/compare timers, and a watchdog.
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properties:
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compatible:
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const: mti,gic
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"#interrupt-cells":
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const: 3
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description: |
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The 1st cell is the type of interrupt: local or shared defined in the
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file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
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GIC interrupt number. The 3d cell encodes the interrupt flags setting up
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the IRQ trigger modes, which are defined in the file
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'dt-bindings/interrupt-controller/irq.h'.
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reg:
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description: |
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Base address and length of the GIC registers space. If not present,
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the base address reported by the hardware GCR_GIC_BASE will be used.
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maxItems: 1
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interrupt-controller: true
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mti,reserved-cpu-vectors:
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description: |
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Specifies the list of CPU interrupt vectors to which the GIC may not
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route interrupts. This property is ignored if the CPU is started in EIC
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mode.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 6
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uniqueItems: true
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items:
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minimum: 2
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maximum: 7
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mti,reserved-ipi-vectors:
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description: |
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Specifies the range of GIC interrupts that are reserved for IPIs.
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It accepts two values: the 1st is the starting interrupt and the 2nd is
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the size of the reserved range. If not specified, the driver will
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allocate the last (2 * number of VPEs in the system).
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- minimum: 0
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maximum: 254
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- minimum: 2
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maximum: 254
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timer:
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type: object
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description: |
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MIPS GIC includes a free-running global timer, per-CPU count/compare
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timers, and a watchdog. Currently only the GIC Timer is supported.
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properties:
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compatible:
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const: mti,gic-timer
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interrupts:
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description: |
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Interrupt for the GIC local timer, so normally it's suppose to be of
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<GIC_LOCAL X IRQ_TYPE_NONE> format.
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maxItems: 1
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clocks:
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maxItems: 1
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clock-frequency: true
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required:
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- compatible
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- interrupts
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oneOf:
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- required:
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- clocks
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- required:
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- clock-frequency
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additionalProperties: false
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additionalProperties: false
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required:
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- compatible
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- "#interrupt-cells"
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- interrupt-controller
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examples:
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- |
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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interrupt-controller@1bdc0000 {
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compatible = "mti,gic";
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reg = <0x1bdc0000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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mti,reserved-cpu-vectors = <7>;
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mti,reserved-ipi-vectors = <40 8>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clock-frequency = <50000000>;
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};
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};
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- |
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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interrupt-controller@1bdc0000 {
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compatible = "mti,gic";
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reg = <0x1bdc0000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&cpu_pll>;
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};
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};
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- |
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interrupt-controller {
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compatible = "mti,gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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...
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