81 lines
1.7 KiB
YAML
81 lines
1.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-mod0-clk.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Allwinner A10 Module 0 Clock Device Tree Bindings
|
|
|
|
maintainers:
|
|
- Chen-Yu Tsai <wens@csie.org>
|
|
- Maxime Ripard <mripard@kernel.org>
|
|
|
|
deprecated: true
|
|
|
|
select:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- allwinner,sun4i-a10-mod0-clk
|
|
- allwinner,sun9i-a80-mod0-clk
|
|
|
|
# The PRCM on the A31 and A23 will have the reg property missing,
|
|
# since it's set at the upper level node, and will be validated by
|
|
# PRCM's schema. Make sure we only validate standalone nodes.
|
|
required:
|
|
- compatible
|
|
- reg
|
|
|
|
properties:
|
|
"#clock-cells":
|
|
const: 0
|
|
|
|
compatible:
|
|
enum:
|
|
- allwinner,sun4i-a10-mod0-clk
|
|
- allwinner,sun9i-a80-mod0-clk
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
# On the A80, the PRCM mod0 clocks have 2 parents.
|
|
minItems: 2
|
|
maxItems: 3
|
|
description: >
|
|
The parent order must match the hardware programming order.
|
|
|
|
clock-output-names:
|
|
maxItems: 1
|
|
|
|
required:
|
|
- "#clock-cells"
|
|
- compatible
|
|
- reg
|
|
- clocks
|
|
- clock-output-names
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
clk@1c20080 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x01c20080 0x4>;
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
clock-output-names = "nand";
|
|
};
|
|
|
|
- |
|
|
clk@8001454 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
|
reg = <0x08001454 0x4>;
|
|
clocks = <&osc32k>, <&osc24M>;
|
|
clock-output-names = "r_ir";
|
|
};
|
|
|
|
...
|