307 lines
7.8 KiB
C
307 lines
7.8 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_GRPH_OBJECT_ID_H__
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#define __DAL_GRPH_OBJECT_ID_H__
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/* Types of graphics objects */
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enum object_type {
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OBJECT_TYPE_UNKNOWN = 0,
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/* Direct ATOM BIOS translation */
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OBJECT_TYPE_GPU,
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OBJECT_TYPE_ENCODER,
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OBJECT_TYPE_CONNECTOR,
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OBJECT_TYPE_ROUTER,
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OBJECT_TYPE_GENERIC,
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/* Driver specific */
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OBJECT_TYPE_AUDIO,
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OBJECT_TYPE_CONTROLLER,
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OBJECT_TYPE_CLOCK_SOURCE,
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OBJECT_TYPE_ENGINE,
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OBJECT_TYPE_COUNT
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};
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/* Enumeration inside one type of graphics objects */
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enum object_enum_id {
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ENUM_ID_UNKNOWN = 0,
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ENUM_ID_1,
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ENUM_ID_2,
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ENUM_ID_3,
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ENUM_ID_4,
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ENUM_ID_5,
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ENUM_ID_6,
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ENUM_ID_7,
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ENUM_ID_COUNT
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};
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/* Generic object ids */
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enum generic_id {
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GENERIC_ID_UNKNOWN = 0,
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GENERIC_ID_MXM_OPM,
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GENERIC_ID_GLSYNC,
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GENERIC_ID_STEREO,
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GENERIC_ID_COUNT
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};
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/* Controller object ids */
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enum controller_id {
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CONTROLLER_ID_UNDEFINED = 0,
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CONTROLLER_ID_D0,
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CONTROLLER_ID_D1,
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CONTROLLER_ID_D2,
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CONTROLLER_ID_D3,
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CONTROLLER_ID_D4,
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CONTROLLER_ID_D5,
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CONTROLLER_ID_UNDERLAY0,
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CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0
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};
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#define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0)
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/*
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* ClockSource object ids.
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* We maintain the order matching (more or less) ATOM BIOS
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* to improve optimized acquire
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*/
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enum clock_source_id {
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CLOCK_SOURCE_ID_UNDEFINED = 0,
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CLOCK_SOURCE_ID_PLL0,
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CLOCK_SOURCE_ID_PLL1,
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CLOCK_SOURCE_ID_PLL2,
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CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */
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CLOCK_SOURCE_ID_DCPLL,
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CLOCK_SOURCE_ID_DFS, /* DENTIST */
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CLOCK_SOURCE_ID_VCE, /* VCE does not need a real PLL */
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/* Used to distinguish between programming pixel clock and ID (Phy) clock */
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CLOCK_SOURCE_ID_DP_DTO,
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CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/
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CLOCK_SOURCE_COMBO_PHY_PLL1,
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CLOCK_SOURCE_COMBO_PHY_PLL2,
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CLOCK_SOURCE_COMBO_PHY_PLL3,
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CLOCK_SOURCE_COMBO_PHY_PLL4,
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CLOCK_SOURCE_COMBO_PHY_PLL5,
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CLOCK_SOURCE_COMBO_DISPLAY_PLL0
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};
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/* Encoder object ids */
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enum encoder_id {
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ENCODER_ID_UNKNOWN = 0,
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/* Radeon Class Display Hardware */
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ENCODER_ID_INTERNAL_LVDS,
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ENCODER_ID_INTERNAL_TMDS1,
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ENCODER_ID_INTERNAL_TMDS2,
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ENCODER_ID_INTERNAL_DAC1,
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ENCODER_ID_INTERNAL_DAC2, /* TV/CV DAC */
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/* External Third Party Encoders */
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ENCODER_ID_INTERNAL_LVTM1, /* not used for Radeon */
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ENCODER_ID_INTERNAL_HDMI,
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/* Kaledisope (KLDSCP) Class Display Hardware */
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ENCODER_ID_INTERNAL_KLDSCP_TMDS1,
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ENCODER_ID_INTERNAL_KLDSCP_DAC1,
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ENCODER_ID_INTERNAL_KLDSCP_DAC2, /* Shared with CV/TV and CRT */
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/* External TMDS (dual link) */
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ENCODER_ID_EXTERNAL_MVPU_FPGA, /* MVPU FPGA chip */
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ENCODER_ID_INTERNAL_DDI,
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ENCODER_ID_INTERNAL_UNIPHY,
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ENCODER_ID_INTERNAL_KLDSCP_LVTMA,
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ENCODER_ID_INTERNAL_UNIPHY1,
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ENCODER_ID_INTERNAL_UNIPHY2,
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ENCODER_ID_EXTERNAL_NUTMEG,
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ENCODER_ID_EXTERNAL_TRAVIS,
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ENCODER_ID_INTERNAL_WIRELESS, /* Internal wireless display encoder */
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ENCODER_ID_INTERNAL_UNIPHY3,
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ENCODER_ID_INTERNAL_VIRTUAL,
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};
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/* Connector object ids */
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enum connector_id {
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CONNECTOR_ID_UNKNOWN = 0,
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CONNECTOR_ID_SINGLE_LINK_DVII = 1,
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CONNECTOR_ID_DUAL_LINK_DVII = 2,
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CONNECTOR_ID_SINGLE_LINK_DVID = 3,
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CONNECTOR_ID_DUAL_LINK_DVID = 4,
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CONNECTOR_ID_VGA = 5,
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CONNECTOR_ID_HDMI_TYPE_A = 12,
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CONNECTOR_ID_LVDS = 14,
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CONNECTOR_ID_PCIE = 16,
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CONNECTOR_ID_HARDCODE_DVI = 18,
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CONNECTOR_ID_DISPLAY_PORT = 19,
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CONNECTOR_ID_EDP = 20,
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CONNECTOR_ID_MXM = 21,
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CONNECTOR_ID_WIRELESS = 22,
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CONNECTOR_ID_MIRACAST = 23,
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CONNECTOR_ID_VIRTUAL = 100
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};
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/* Audio object ids */
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enum audio_id {
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AUDIO_ID_UNKNOWN = 0,
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AUDIO_ID_INTERNAL_AZALIA
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};
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/* Engine object ids */
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enum engine_id {
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ENGINE_ID_DIGA,
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ENGINE_ID_DIGB,
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ENGINE_ID_DIGC,
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ENGINE_ID_DIGD,
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ENGINE_ID_DIGE,
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ENGINE_ID_DIGF,
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ENGINE_ID_DIGG,
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ENGINE_ID_DACA,
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ENGINE_ID_DACB,
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ENGINE_ID_VCE, /* wireless display pseudo-encoder */
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ENGINE_ID_VIRTUAL,
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ENGINE_ID_COUNT,
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ENGINE_ID_UNKNOWN = (-1L)
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};
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enum transmitter_color_depth {
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TRANSMITTER_COLOR_DEPTH_24 = 0, /* 8 bits */
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TRANSMITTER_COLOR_DEPTH_30, /* 10 bits */
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TRANSMITTER_COLOR_DEPTH_36, /* 12 bits */
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TRANSMITTER_COLOR_DEPTH_48 /* 16 bits */
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};
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enum dp_alt_mode {
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DP_Alt_mode__Unknown = 0,
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DP_Alt_mode__Connect,
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DP_Alt_mode__NoConnect,
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};
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/*
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*****************************************************************************
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* graphics_object_id struct
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*
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* graphics_object_id is a very simple struct wrapping 32bit Graphics
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* Object identication
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*
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* This struct should stay very simple
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* No dependencies at all (no includes)
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* No debug messages or asserts
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* No #ifndef and preprocessor directives
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* No grow in space (no more data member)
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*****************************************************************************
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*/
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struct graphics_object_id {
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uint32_t id:8;
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uint32_t enum_id:4;
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uint32_t type:4;
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uint32_t reserved:16; /* for padding. total size should be u32 */
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};
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/* some simple functions for convenient graphics_object_id handle */
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static inline struct graphics_object_id dal_graphics_object_id_init(
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uint32_t id,
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enum object_enum_id enum_id,
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enum object_type type)
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{
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struct graphics_object_id result = {
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id, enum_id, type, 0
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};
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return result;
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}
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/* Based on internal data members memory layout */
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static inline uint32_t dal_graphics_object_id_to_uint(
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struct graphics_object_id id)
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{
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return id.id + (id.enum_id << 0x8) + (id.type << 0xc);
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}
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static inline enum controller_id dal_graphics_object_id_get_controller_id(
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struct graphics_object_id id)
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{
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if (id.type == OBJECT_TYPE_CONTROLLER)
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return (enum controller_id) id.id;
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return CONTROLLER_ID_UNDEFINED;
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}
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static inline enum clock_source_id dal_graphics_object_id_get_clock_source_id(
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struct graphics_object_id id)
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{
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if (id.type == OBJECT_TYPE_CLOCK_SOURCE)
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return (enum clock_source_id) id.id;
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return CLOCK_SOURCE_ID_UNDEFINED;
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}
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static inline enum encoder_id dal_graphics_object_id_get_encoder_id(
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struct graphics_object_id id)
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{
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if (id.type == OBJECT_TYPE_ENCODER)
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return (enum encoder_id) id.id;
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return ENCODER_ID_UNKNOWN;
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}
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static inline enum connector_id dal_graphics_object_id_get_connector_id(
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struct graphics_object_id id)
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{
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if (id.type == OBJECT_TYPE_CONNECTOR)
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return (enum connector_id) id.id;
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return CONNECTOR_ID_UNKNOWN;
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}
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static inline enum audio_id dal_graphics_object_id_get_audio_id(
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struct graphics_object_id id)
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{
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if (id.type == OBJECT_TYPE_AUDIO)
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return (enum audio_id) id.id;
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return AUDIO_ID_UNKNOWN;
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}
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static inline enum engine_id dal_graphics_object_id_get_engine_id(
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struct graphics_object_id id)
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{
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if (id.type == OBJECT_TYPE_ENGINE)
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return (enum engine_id) id.id;
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return ENGINE_ID_UNKNOWN;
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}
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static inline bool dal_graphics_object_id_equal(
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struct graphics_object_id id_1,
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struct graphics_object_id id_2)
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{
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if ((id_1.id == id_2.id) && (id_1.enum_id == id_2.enum_id) &&
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(id_1.type == id_2.type)) {
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return true;
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}
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return false;
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}
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#endif
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