388 lines
10 KiB
C
388 lines
10 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "nbio/nbio_6_1_offset.h"
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#include "nbio/nbio_6_1_sh_mask.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_sh_mask.h"
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#include "mp/mp_9_0_offset.h"
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#include "soc15.h"
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#include "vega10_ih.h"
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#include "soc15_common.h"
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#include "mxgpu_ai.h"
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static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev)
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{
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WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
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}
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static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val)
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{
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WREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE, val ? 1 : 0);
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}
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/*
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* this peek_msg could *only* be called in IRQ routine becuase in IRQ routine
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* RCV_MSG_VALID filed of BIF_BX_PF0_MAILBOX_CONTROL must already be set to 1
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* by host.
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*
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* if called no in IRQ routine, this peek_msg cannot guaranteed to return the
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* correct value since it doesn't return the RCV_DW0 under the case that
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* RCV_MSG_VALID is set by host.
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*/
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static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev)
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{
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return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0));
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}
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static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev,
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enum idh_event event)
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{
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u32 reg;
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0));
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if (reg != event)
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return -ENOENT;
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xgpu_ai_mailbox_send_ack(adev);
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return 0;
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}
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static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) {
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return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2;
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}
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static int xgpu_ai_poll_ack(struct amdgpu_device *adev)
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{
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int timeout = AI_MAILBOX_POLL_ACK_TIMEDOUT;
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u8 reg;
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do {
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reg = RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE);
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if (reg & 2)
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return 0;
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mdelay(5);
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timeout -= 5;
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} while (timeout > 1);
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pr_err("Doesn't get TRN_MSG_ACK from pf in %d msec\n", AI_MAILBOX_POLL_ACK_TIMEDOUT);
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return -ETIME;
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}
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static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event)
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{
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int r, timeout = AI_MAILBOX_POLL_MSG_TIMEDOUT;
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do {
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r = xgpu_ai_mailbox_rcv_msg(adev, event);
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if (!r)
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return 0;
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msleep(10);
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timeout -= 10;
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} while (timeout > 1);
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pr_err("Doesn't get msg:%d from pf, error=%d\n", event, r);
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return -ETIME;
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}
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static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,
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enum idh_request req, u32 data1, u32 data2, u32 data3) {
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u32 reg;
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int r;
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uint8_t trn;
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/* IMPORTANT:
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* clear TRN_MSG_VALID valid to clear host's RCV_MSG_ACK
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* and with host's RCV_MSG_ACK cleared hw automatically clear host's RCV_MSG_ACK
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* which lead to VF's TRN_MSG_ACK cleared, otherwise below xgpu_ai_poll_ack()
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* will return immediatly
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*/
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do {
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xgpu_ai_mailbox_set_valid(adev, false);
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trn = xgpu_ai_peek_ack(adev);
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if (trn) {
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pr_err("trn=%x ACK should not assert! wait again !\n", trn);
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msleep(1);
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}
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} while(trn);
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reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0));
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reg = REG_SET_FIELD(reg, BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0,
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MSGBUF_DATA, req);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0),
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reg);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1),
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data1);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2),
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data2);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3),
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data3);
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xgpu_ai_mailbox_set_valid(adev, true);
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/* start to poll ack */
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r = xgpu_ai_poll_ack(adev);
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if (r)
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pr_err("Doesn't get ack from pf, continue\n");
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xgpu_ai_mailbox_set_valid(adev, false);
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}
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static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
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enum idh_request req)
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{
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int r;
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xgpu_ai_mailbox_trans_msg(adev, req, 0, 0, 0);
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/* start to check msg if request is idh_req_gpu_init_access */
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if (req == IDH_REQ_GPU_INIT_ACCESS ||
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req == IDH_REQ_GPU_FINI_ACCESS ||
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req == IDH_REQ_GPU_RESET_ACCESS) {
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r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU);
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if (r) {
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pr_err("Doesn't get READY_TO_ACCESS_GPU from pf, give up\n");
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return r;
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}
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/* Retrieve checksum from mailbox2 */
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if (req == IDH_REQ_GPU_INIT_ACCESS || req == IDH_REQ_GPU_RESET_ACCESS) {
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adev->virt.fw_reserve.checksum_key =
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RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
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mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
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}
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}
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return 0;
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}
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static int xgpu_ai_request_reset(struct amdgpu_device *adev)
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{
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int ret, i = 0;
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while (i < AI_MAILBOX_POLL_MSG_REP_MAX) {
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ret = xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS);
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if (!ret)
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break;
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i++;
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}
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return ret;
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}
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static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev,
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bool init)
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{
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enum idh_request req;
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req = init ? IDH_REQ_GPU_INIT_ACCESS : IDH_REQ_GPU_FINI_ACCESS;
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return xgpu_ai_send_access_requests(adev, req);
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}
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static int xgpu_ai_release_full_gpu_access(struct amdgpu_device *adev,
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bool init)
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{
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enum idh_request req;
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int r = 0;
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req = init ? IDH_REL_GPU_INIT_ACCESS : IDH_REL_GPU_FINI_ACCESS;
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r = xgpu_ai_send_access_requests(adev, req);
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return r;
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}
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static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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DRM_DEBUG("get ack intr and do nothing.\n");
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return 0;
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}
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static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, ACK_INT_EN,
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(state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
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return 0;
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}
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static void xgpu_ai_mailbox_flr_work(struct work_struct *work)
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{
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struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);
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struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);
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int timeout = AI_MAILBOX_POLL_FLR_TIMEDOUT;
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/* block amdgpu_gpu_recover till msg FLR COMPLETE received,
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* otherwise the mailbox msg will be ruined/reseted by
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* the VF FLR.
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*/
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if (!down_read_trylock(&adev->reset_sem))
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return;
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amdgpu_virt_fini_data_exchange(adev);
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atomic_set(&adev->in_gpu_reset, 1);
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do {
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if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL)
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goto flr_done;
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msleep(10);
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timeout -= 10;
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} while (timeout > 1);
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flr_done:
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atomic_set(&adev->in_gpu_reset, 0);
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up_read(&adev->reset_sem);
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/* Trigger recovery for world switch failure if no TDR */
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if (amdgpu_device_should_recover_gpu(adev)
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&& (!amdgpu_device_has_job_running(adev) ||
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adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT))
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amdgpu_device_gpu_recover(adev, NULL);
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}
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static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_MAILBOX_INT_CNTL, VALID_INT_EN,
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(state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0);
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WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
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return 0;
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}
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static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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enum idh_event event = xgpu_ai_mailbox_peek_msg(adev);
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switch (event) {
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case IDH_FLR_NOTIFICATION:
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if (amdgpu_sriov_runtime(adev))
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schedule_work(&adev->virt.flr_work);
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break;
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case IDH_QUERY_ALIVE:
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xgpu_ai_mailbox_send_ack(adev);
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break;
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/* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
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* it byfar since that polling thread will handle it,
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* other msg like flr complete is not handled here.
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*/
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case IDH_CLR_MSG_BUF:
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case IDH_FLR_NOTIFICATION_CMPL:
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case IDH_READY_TO_ACCESS_GPU:
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default:
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break;
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}
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return 0;
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}
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static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_ack_irq_funcs = {
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.set = xgpu_ai_set_mailbox_ack_irq,
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.process = xgpu_ai_mailbox_ack_irq,
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};
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static const struct amdgpu_irq_src_funcs xgpu_ai_mailbox_rcv_irq_funcs = {
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.set = xgpu_ai_set_mailbox_rcv_irq,
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.process = xgpu_ai_mailbox_rcv_irq,
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};
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void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev)
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{
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adev->virt.ack_irq.num_types = 1;
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adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs;
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adev->virt.rcv_irq.num_types = 1;
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adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs;
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}
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int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev)
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{
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int r;
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);
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if (r)
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return r;
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r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);
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if (r) {
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amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
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return r;
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}
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return 0;
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}
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int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev)
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{
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int r;
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r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);
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if (r)
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return r;
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r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);
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if (r) {
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amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
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return r;
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}
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INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work);
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return 0;
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}
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void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)
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{
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amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);
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amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
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}
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const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
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.req_full_gpu = xgpu_ai_request_full_gpu_access,
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.rel_full_gpu = xgpu_ai_release_full_gpu_access,
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.reset_gpu = xgpu_ai_request_reset,
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.wait_reset = NULL,
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.trans_msg = xgpu_ai_mailbox_trans_msg,
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};
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