439 lines
12 KiB
C
439 lines
12 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_discovery.h"
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#include "soc15_hw_ip.h"
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#include "discovery.h"
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#define mmRCC_CONFIG_MEMSIZE 0xde3
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#define mmMM_INDEX 0x0
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#define mmMM_INDEX_HI 0x6
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#define mmMM_DATA 0x1
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#define HW_ID_MAX 300
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static const char *hw_id_names[HW_ID_MAX] = {
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[MP1_HWID] = "MP1",
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[MP2_HWID] = "MP2",
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[THM_HWID] = "THM",
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[SMUIO_HWID] = "SMUIO",
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[FUSE_HWID] = "FUSE",
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[CLKA_HWID] = "CLKA",
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[PWR_HWID] = "PWR",
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[GC_HWID] = "GC",
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[UVD_HWID] = "UVD",
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[AUDIO_AZ_HWID] = "AUDIO_AZ",
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[ACP_HWID] = "ACP",
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[DCI_HWID] = "DCI",
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[DMU_HWID] = "DMU",
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[DCO_HWID] = "DCO",
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[DIO_HWID] = "DIO",
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[XDMA_HWID] = "XDMA",
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[DCEAZ_HWID] = "DCEAZ",
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[DAZ_HWID] = "DAZ",
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[SDPMUX_HWID] = "SDPMUX",
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[NTB_HWID] = "NTB",
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[IOHC_HWID] = "IOHC",
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[L2IMU_HWID] = "L2IMU",
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[VCE_HWID] = "VCE",
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[MMHUB_HWID] = "MMHUB",
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[ATHUB_HWID] = "ATHUB",
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[DBGU_NBIO_HWID] = "DBGU_NBIO",
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[DFX_HWID] = "DFX",
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[DBGU0_HWID] = "DBGU0",
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[DBGU1_HWID] = "DBGU1",
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[OSSSYS_HWID] = "OSSSYS",
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[HDP_HWID] = "HDP",
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[SDMA0_HWID] = "SDMA0",
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[SDMA1_HWID] = "SDMA1",
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[ISP_HWID] = "ISP",
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[DBGU_IO_HWID] = "DBGU_IO",
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[DF_HWID] = "DF",
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[CLKB_HWID] = "CLKB",
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[FCH_HWID] = "FCH",
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[DFX_DAP_HWID] = "DFX_DAP",
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[L1IMU_PCIE_HWID] = "L1IMU_PCIE",
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[L1IMU_NBIF_HWID] = "L1IMU_NBIF",
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[L1IMU_IOAGR_HWID] = "L1IMU_IOAGR",
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[L1IMU3_HWID] = "L1IMU3",
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[L1IMU4_HWID] = "L1IMU4",
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[L1IMU5_HWID] = "L1IMU5",
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[L1IMU6_HWID] = "L1IMU6",
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[L1IMU7_HWID] = "L1IMU7",
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[L1IMU8_HWID] = "L1IMU8",
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[L1IMU9_HWID] = "L1IMU9",
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[L1IMU10_HWID] = "L1IMU10",
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[L1IMU11_HWID] = "L1IMU11",
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[L1IMU12_HWID] = "L1IMU12",
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[L1IMU13_HWID] = "L1IMU13",
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[L1IMU14_HWID] = "L1IMU14",
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[L1IMU15_HWID] = "L1IMU15",
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[WAFLC_HWID] = "WAFLC",
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[FCH_USB_PD_HWID] = "FCH_USB_PD",
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[PCIE_HWID] = "PCIE",
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[PCS_HWID] = "PCS",
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[DDCL_HWID] = "DDCL",
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[SST_HWID] = "SST",
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[IOAGR_HWID] = "IOAGR",
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[NBIF_HWID] = "NBIF",
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[IOAPIC_HWID] = "IOAPIC",
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[SYSTEMHUB_HWID] = "SYSTEMHUB",
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[NTBCCP_HWID] = "NTBCCP",
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[UMC_HWID] = "UMC",
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[SATA_HWID] = "SATA",
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[USB_HWID] = "USB",
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[CCXSEC_HWID] = "CCXSEC",
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[XGMI_HWID] = "XGMI",
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[XGBE_HWID] = "XGBE",
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[MP0_HWID] = "MP0",
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};
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static int hw_id_map[MAX_HWIP] = {
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[GC_HWIP] = GC_HWID,
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[HDP_HWIP] = HDP_HWID,
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[SDMA0_HWIP] = SDMA0_HWID,
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[SDMA1_HWIP] = SDMA1_HWID,
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[MMHUB_HWIP] = MMHUB_HWID,
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[ATHUB_HWIP] = ATHUB_HWID,
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[NBIO_HWIP] = NBIF_HWID,
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[MP0_HWIP] = MP0_HWID,
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[MP1_HWIP] = MP1_HWID,
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[UVD_HWIP] = UVD_HWID,
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[VCE_HWIP] = VCE_HWID,
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[DF_HWIP] = DF_HWID,
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[DCE_HWIP] = DMU_HWID,
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[OSSSYS_HWIP] = OSSSYS_HWID,
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[SMUIO_HWIP] = SMUIO_HWID,
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[PWR_HWIP] = PWR_HWID,
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[NBIF_HWIP] = NBIF_HWID,
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[THM_HWIP] = THM_HWID,
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[CLK_HWIP] = CLKA_HWID,
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[UMC_HWIP] = UMC_HWID,
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};
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static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
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{
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uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
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uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
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amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
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adev->mman.discovery_tmr_size, false);
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return 0;
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}
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static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
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{
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uint16_t checksum = 0;
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int i;
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for (i = 0; i < size; i++)
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checksum += data[i];
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return checksum;
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}
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static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
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uint16_t expected)
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{
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return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
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}
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static int amdgpu_discovery_init(struct amdgpu_device *adev)
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{
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struct table_info *info;
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struct binary_header *bhdr;
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struct ip_discovery_header *ihdr;
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struct gpu_info_header *ghdr;
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uint16_t offset;
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uint16_t size;
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uint16_t checksum;
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int r;
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adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
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adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
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if (!adev->mman.discovery_bin)
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return -ENOMEM;
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r = amdgpu_discovery_read_binary(adev, adev->mman.discovery_bin);
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if (r) {
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DRM_ERROR("failed to read ip discovery binary\n");
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goto out;
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}
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bhdr = (struct binary_header *)adev->mman.discovery_bin;
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if (le32_to_cpu(bhdr->binary_signature) != BINARY_SIGNATURE) {
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DRM_ERROR("invalid ip discovery binary signature\n");
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r = -EINVAL;
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goto out;
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}
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offset = offsetof(struct binary_header, binary_checksum) +
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sizeof(bhdr->binary_checksum);
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size = bhdr->binary_size - offset;
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checksum = bhdr->binary_checksum;
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if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
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size, checksum)) {
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DRM_ERROR("invalid ip discovery binary checksum\n");
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r = -EINVAL;
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goto out;
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}
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info = &bhdr->table_list[IP_DISCOVERY];
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offset = le16_to_cpu(info->offset);
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checksum = le16_to_cpu(info->checksum);
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ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
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if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
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DRM_ERROR("invalid ip discovery data table signature\n");
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r = -EINVAL;
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goto out;
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}
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if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
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ihdr->size, checksum)) {
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DRM_ERROR("invalid ip discovery data table checksum\n");
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r = -EINVAL;
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goto out;
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}
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info = &bhdr->table_list[GC];
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offset = le16_to_cpu(info->offset);
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checksum = le16_to_cpu(info->checksum);
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ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
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if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
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ghdr->size, checksum)) {
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DRM_ERROR("invalid gc data table checksum\n");
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r = -EINVAL;
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goto out;
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}
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return 0;
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out:
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kfree(adev->mman.discovery_bin);
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adev->mman.discovery_bin = NULL;
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return r;
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}
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void amdgpu_discovery_fini(struct amdgpu_device *adev)
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{
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kfree(adev->mman.discovery_bin);
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adev->mman.discovery_bin = NULL;
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}
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int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
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{
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struct binary_header *bhdr;
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struct ip_discovery_header *ihdr;
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struct die_header *dhdr;
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struct ip *ip;
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uint16_t die_offset;
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uint16_t ip_offset;
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uint16_t num_dies;
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uint16_t num_ips;
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uint8_t num_base_address;
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int hw_ip;
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int i, j, k;
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int r;
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r = amdgpu_discovery_init(adev);
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if (r) {
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DRM_ERROR("amdgpu_discovery_init failed\n");
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return r;
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}
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bhdr = (struct binary_header *)adev->mman.discovery_bin;
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ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
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le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
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num_dies = le16_to_cpu(ihdr->num_dies);
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DRM_DEBUG("number of dies: %d\n", num_dies);
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for (i = 0; i < num_dies; i++) {
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die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
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dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
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num_ips = le16_to_cpu(dhdr->num_ips);
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ip_offset = die_offset + sizeof(*dhdr);
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if (le16_to_cpu(dhdr->die_id) != i) {
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DRM_ERROR("invalid die id %d, expected %d\n",
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le16_to_cpu(dhdr->die_id), i);
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return -EINVAL;
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}
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DRM_DEBUG("number of hardware IPs on die%d: %d\n",
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le16_to_cpu(dhdr->die_id), num_ips);
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for (j = 0; j < num_ips; j++) {
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ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
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num_base_address = ip->num_base_address;
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DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
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hw_id_names[le16_to_cpu(ip->hw_id)],
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le16_to_cpu(ip->hw_id),
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ip->number_instance,
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ip->major, ip->minor,
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ip->revision);
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for (k = 0; k < num_base_address; k++) {
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/*
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* convert the endianness of base addresses in place,
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* so that we don't need to convert them when accessing adev->reg_offset.
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*/
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ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
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DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
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}
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for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
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if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
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DRM_DEBUG("set register base offset for %s\n",
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hw_id_names[le16_to_cpu(ip->hw_id)]);
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adev->reg_offset[hw_ip][ip->number_instance] =
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ip->base_address;
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}
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}
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ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
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}
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}
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return 0;
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}
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int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,
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int *major, int *minor, int *revision)
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{
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struct binary_header *bhdr;
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struct ip_discovery_header *ihdr;
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struct die_header *dhdr;
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struct ip *ip;
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uint16_t die_offset;
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uint16_t ip_offset;
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uint16_t num_dies;
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uint16_t num_ips;
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int i, j;
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if (!adev->mman.discovery_bin) {
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DRM_ERROR("ip discovery uninitialized\n");
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return -EINVAL;
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}
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bhdr = (struct binary_header *)adev->mman.discovery_bin;
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ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
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le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
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num_dies = le16_to_cpu(ihdr->num_dies);
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for (i = 0; i < num_dies; i++) {
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die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
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dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
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num_ips = le16_to_cpu(dhdr->num_ips);
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ip_offset = die_offset + sizeof(*dhdr);
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for (j = 0; j < num_ips; j++) {
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ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
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if (le16_to_cpu(ip->hw_id) == hw_id) {
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if (major)
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*major = ip->major;
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if (minor)
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*minor = ip->minor;
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if (revision)
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*revision = ip->revision;
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return 0;
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}
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ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
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}
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}
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return -EINVAL;
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}
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void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
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{
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struct binary_header *bhdr;
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struct harvest_table *harvest_info;
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int i;
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bhdr = (struct binary_header *)adev->mman.discovery_bin;
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harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
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le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
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for (i = 0; i < 32; i++) {
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if (le32_to_cpu(harvest_info->list[i].hw_id) == 0)
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break;
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switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
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case VCN_HWID:
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adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
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adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
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break;
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case DMU_HWID:
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adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
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break;
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default:
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break;
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}
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}
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}
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int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
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{
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struct binary_header *bhdr;
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struct gc_info_v1_0 *gc_info;
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if (!adev->mman.discovery_bin) {
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DRM_ERROR("ip discovery uninitialized\n");
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return -EINVAL;
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}
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bhdr = (struct binary_header *)adev->mman.discovery_bin;
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gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +
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le16_to_cpu(bhdr->table_list[GC].offset));
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adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
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adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
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le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
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adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
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adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
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adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
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adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
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adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
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adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
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adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
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adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
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adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
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adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
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adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
|
|
adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
|
|
adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
|
|
le32_to_cpu(gc_info->gc_num_sa_per_se);
|
|
adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
|
|
|
|
return 0;
|
|
}
|