145 lines
3.1 KiB
C
145 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* H8S2678 clock driver
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*
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* Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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static DEFINE_SPINLOCK(clklock);
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#define MAX_FREQ 33333333
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#define MIN_FREQ 8000000
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struct pll_clock {
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struct clk_hw hw;
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void __iomem *sckcr;
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void __iomem *pllcr;
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};
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#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
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static unsigned long pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pll_clock *pll_clock = to_pll_clock(hw);
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int mul = 1 << (readb(pll_clock->pllcr) & 3);
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return parent_rate * mul;
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}
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static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int i, m = -1;
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long offset[3];
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if (rate > MAX_FREQ)
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rate = MAX_FREQ;
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if (rate < MIN_FREQ)
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rate = MIN_FREQ;
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for (i = 0; i < 3; i++)
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offset[i] = abs(rate - (*prate * (1 << i)));
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for (i = 0; i < 3; i++)
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if (m < 0)
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m = i;
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else
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m = (offset[i] < offset[m])?i:m;
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return *prate * (1 << m);
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}
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static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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int pll;
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unsigned char val;
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unsigned long flags;
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struct pll_clock *pll_clock = to_pll_clock(hw);
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pll = ((rate / parent_rate) / 2) & 0x03;
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spin_lock_irqsave(&clklock, flags);
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val = readb(pll_clock->sckcr);
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val |= 0x08;
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writeb(val, pll_clock->sckcr);
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val = readb(pll_clock->pllcr);
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val &= ~0x03;
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val |= pll;
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writeb(val, pll_clock->pllcr);
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spin_unlock_irqrestore(&clklock, flags);
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return 0;
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}
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static const struct clk_ops pll_ops = {
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.recalc_rate = pll_recalc_rate,
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.round_rate = pll_round_rate,
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.set_rate = pll_set_rate,
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};
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static void __init h8s2678_pll_clk_setup(struct device_node *node)
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{
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unsigned int num_parents;
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const char *clk_name = node->name;
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const char *parent_name;
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struct pll_clock *pll_clock;
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struct clk_init_data init;
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int ret;
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num_parents = of_clk_get_parent_count(node);
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if (!num_parents) {
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pr_err("%s: no parent found", clk_name);
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return;
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}
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pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
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if (!pll_clock)
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return;
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pll_clock->sckcr = of_iomap(node, 0);
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if (pll_clock->sckcr == NULL) {
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pr_err("%s: failed to map divide register", clk_name);
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goto free_clock;
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}
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pll_clock->pllcr = of_iomap(node, 1);
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if (pll_clock->pllcr == NULL) {
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pr_err("%s: failed to map multiply register", clk_name);
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goto unmap_sckcr;
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}
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parent_name = of_clk_get_parent_name(node, 0);
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init.name = clk_name;
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init.ops = &pll_ops;
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init.flags = CLK_IS_BASIC;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pll_clock->hw.init = &init;
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ret = clk_hw_register(NULL, &pll_clock->hw);
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if (ret) {
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pr_err("%s: failed to register %s div clock (%d)\n",
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__func__, clk_name, ret);
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goto unmap_pllcr;
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}
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of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
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return;
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unmap_pllcr:
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iounmap(pll_clock->pllcr);
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unmap_sckcr:
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iounmap(pll_clock->sckcr);
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free_clock:
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kfree(pll_clock);
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}
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CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
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h8s2678_pll_clk_setup);
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