229 lines
6.0 KiB
C
229 lines
6.0 KiB
C
/*
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* RNG driver for VIA RNGs
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*
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* Copyright 2005 (c) MontaVista Software, Inc.
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*
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* with the majority of the code coming from:
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*
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* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
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* (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
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*
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* derived from
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*
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* Hardware driver for the AMD 768 Random Number Generator (RNG)
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* (c) Copyright 2001 Red Hat Inc
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*
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* derived from
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*
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* Hardware driver for Intel i810 Random Number Generator (RNG)
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* Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
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* Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <crypto/padlock.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/hw_random.h>
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#include <linux/delay.h>
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#include <asm/cpu_device_id.h>
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#include <asm/io.h>
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#include <asm/msr.h>
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#include <asm/cpufeature.h>
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#include <asm/fpu/api.h>
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enum {
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VIA_STRFILT_CNT_SHIFT = 16,
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VIA_STRFILT_FAIL = (1 << 15),
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VIA_STRFILT_ENABLE = (1 << 14),
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VIA_RAWBITS_ENABLE = (1 << 13),
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VIA_RNG_ENABLE = (1 << 6),
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VIA_NOISESRC1 = (1 << 8),
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VIA_NOISESRC2 = (1 << 9),
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VIA_XSTORE_CNT_MASK = 0x0F,
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VIA_RNG_CHUNK_8 = 0x00, /* 64 rand bits, 64 stored bits */
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VIA_RNG_CHUNK_4 = 0x01, /* 32 rand bits, 32 stored bits */
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VIA_RNG_CHUNK_4_MASK = 0xFFFFFFFF,
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VIA_RNG_CHUNK_2 = 0x02, /* 16 rand bits, 32 stored bits */
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VIA_RNG_CHUNK_2_MASK = 0xFFFF,
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VIA_RNG_CHUNK_1 = 0x03, /* 8 rand bits, 32 stored bits */
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VIA_RNG_CHUNK_1_MASK = 0xFF,
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};
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/*
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* Investigate using the 'rep' prefix to obtain 32 bits of random data
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* in one insn. The upside is potentially better performance. The
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* downside is that the instruction becomes no longer atomic. Due to
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* this, just like familiar issues with /dev/random itself, the worst
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* case of a 'rep xstore' could potentially pause a cpu for an
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* unreasonably long time. In practice, this condition would likely
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* only occur when the hardware is failing. (or so we hope :))
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*
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* Another possible performance boost may come from simply buffering
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* until we have 4 bytes, thus returning a u32 at a time,
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* instead of the current u8-at-a-time.
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*
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* Padlock instructions can generate a spurious DNA fault, but the
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* kernel doesn't use CR0.TS, so this doesn't matter.
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*/
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static inline u32 xstore(u32 *addr, u32 edx_in)
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{
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u32 eax_out;
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asm(".byte 0x0F,0xA7,0xC0 /* xstore %%edi (addr=%0) */"
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: "=m" (*addr), "=a" (eax_out), "+d" (edx_in), "+D" (addr));
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return eax_out;
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}
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static int via_rng_data_present(struct hwrng *rng, int wait)
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{
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char buf[16 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__
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((aligned(STACK_ALIGN)));
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u32 *via_rng_datum = (u32 *)PTR_ALIGN(&buf[0], PADLOCK_ALIGNMENT);
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u32 bytes_out;
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int i;
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/* We choose the recommended 1-byte-per-instruction RNG rate,
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* for greater randomness at the expense of speed. Larger
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* values 2, 4, or 8 bytes-per-instruction yield greater
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* speed at lesser randomness.
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*
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* If you change this to another VIA_CHUNK_n, you must also
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* change the ->n_bytes values in rng_vendor_ops[] tables.
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* VIA_CHUNK_8 requires further code changes.
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*
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* A copy of MSR_VIA_RNG is placed in eax_out when xstore
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* completes.
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*/
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for (i = 0; i < 20; i++) {
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*via_rng_datum = 0; /* paranoia, not really necessary */
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bytes_out = xstore(via_rng_datum, VIA_RNG_CHUNK_1);
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bytes_out &= VIA_XSTORE_CNT_MASK;
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if (bytes_out || !wait)
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break;
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udelay(10);
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}
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rng->priv = *via_rng_datum;
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return bytes_out ? 1 : 0;
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}
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static int via_rng_data_read(struct hwrng *rng, u32 *data)
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{
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u32 via_rng_datum = (u32)rng->priv;
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*data = via_rng_datum;
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return 1;
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}
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static int via_rng_init(struct hwrng *rng)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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u32 lo, hi, old_lo;
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/* VIA Nano CPUs don't have the MSR_VIA_RNG anymore. The RNG
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* is always enabled if CPUID rng_en is set. There is no
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* RNG configuration like it used to be the case in this
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* register */
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if ((c->x86 == 6) && (c->x86_model >= 0x0f)) {
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if (!boot_cpu_has(X86_FEATURE_XSTORE_EN)) {
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pr_err(PFX "can't enable hardware RNG "
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"if XSTORE is not enabled\n");
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return -ENODEV;
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}
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return 0;
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}
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/* Control the RNG via MSR. Tread lightly and pay very close
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* close attention to values written, as the reserved fields
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* are documented to be "undefined and unpredictable"; but it
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* does not say to write them as zero, so I make a guess that
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* we restore the values we find in the register.
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*/
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rdmsr(MSR_VIA_RNG, lo, hi);
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old_lo = lo;
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lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT);
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lo &= ~VIA_XSTORE_CNT_MASK;
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lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE);
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lo |= VIA_RNG_ENABLE;
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lo |= VIA_NOISESRC1;
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/* Enable secondary noise source on CPUs where it is present. */
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/* Nehemiah stepping 8 and higher */
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if ((c->x86_model == 9) && (c->x86_mask > 7))
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lo |= VIA_NOISESRC2;
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/* Esther */
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if (c->x86_model >= 10)
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lo |= VIA_NOISESRC2;
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if (lo != old_lo)
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wrmsr(MSR_VIA_RNG, lo, hi);
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/* perhaps-unnecessary sanity check; remove after testing if
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unneeded */
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rdmsr(MSR_VIA_RNG, lo, hi);
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if ((lo & VIA_RNG_ENABLE) == 0) {
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pr_err(PFX "cannot enable VIA C3 RNG, aborting\n");
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return -ENODEV;
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}
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return 0;
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}
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static struct hwrng via_rng = {
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.name = "via",
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.init = via_rng_init,
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.data_present = via_rng_data_present,
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.data_read = via_rng_data_read,
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};
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static int __init mod_init(void)
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{
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int err;
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if (!boot_cpu_has(X86_FEATURE_XSTORE))
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return -ENODEV;
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pr_info("VIA RNG detected\n");
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err = hwrng_register(&via_rng);
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if (err) {
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pr_err(PFX "RNG registering failed (%d)\n",
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err);
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goto out;
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}
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out:
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return err;
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}
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static void __exit mod_exit(void)
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{
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hwrng_unregister(&via_rng);
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}
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module_init(mod_init);
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module_exit(mod_exit);
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static struct x86_cpu_id __maybe_unused via_rng_cpu_id[] = {
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X86_FEATURE_MATCH(X86_FEATURE_XSTORE),
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{}
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};
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MODULE_DESCRIPTION("H/W RNG driver for VIA CPU with PadLock");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(x86cpu, via_rng_cpu_id);
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