588 lines
18 KiB
C
588 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2020 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef CPUCP_IF_H
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#define CPUCP_IF_H
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#include <linux/types.h>
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#include <linux/if_ether.h>
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#define NUM_HBM_PSEUDO_CH 2
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#define NUM_HBM_CH_PER_DEV 8
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#define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0
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#define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001
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#define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1
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#define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002
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#define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2
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#define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004
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#define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3
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#define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008
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#define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4
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#define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010
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#define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5
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#define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020
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#define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6
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#define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0
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/*
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* info of the pkt queue pointers in the first async occurrence
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*/
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struct cpucp_pkt_sync_err {
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__le32 pi;
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__le32 ci;
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};
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struct hl_eq_hbm_ecc_data {
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/* SERR counter */
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__le32 sec_cnt;
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/* DERR counter */
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__le32 dec_cnt;
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/* Supplemental Information according to the mask bits */
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__le32 hbm_ecc_info;
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/* Address in hbm where the ecc happened */
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__le32 first_addr;
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/* SERR continuous address counter */
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__le32 sec_cont_cnt;
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__le32 pad;
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};
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/*
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* EVENT QUEUE
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*/
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struct hl_eq_header {
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__le32 reserved;
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__le32 ctl;
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};
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struct hl_eq_ecc_data {
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__le64 ecc_address;
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__le64 ecc_syndrom;
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__u8 memory_wrapper_idx;
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__u8 pad[7];
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};
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enum hl_sm_sei_cause {
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SM_SEI_SO_OVERFLOW,
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SM_SEI_LBW_4B_UNALIGNED,
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SM_SEI_AXI_RESPONSE_ERR
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};
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struct hl_eq_sm_sei_data {
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__le32 sei_log;
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/* enum hl_sm_sei_cause */
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__u8 sei_cause;
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__u8 pad[3];
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};
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struct hl_eq_entry {
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struct hl_eq_header hdr;
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union {
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struct hl_eq_ecc_data ecc_data;
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struct hl_eq_hbm_ecc_data hbm_ecc_data;
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struct hl_eq_sm_sei_data sm_sei_data;
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struct cpucp_pkt_sync_err pkt_sync_err;
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__le64 data[7];
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};
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};
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#define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry)
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#define EQ_CTL_READY_SHIFT 31
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#define EQ_CTL_READY_MASK 0x80000000
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#define EQ_CTL_EVENT_TYPE_SHIFT 16
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#define EQ_CTL_EVENT_TYPE_MASK 0x03FF0000
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enum pq_init_status {
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PQ_INIT_STATUS_NA = 0,
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PQ_INIT_STATUS_READY_FOR_CP,
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PQ_INIT_STATUS_READY_FOR_HOST,
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PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI
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};
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/*
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* CpuCP Primary Queue Packets
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*
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* During normal operation, the host's kernel driver needs to send various
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* messages to CpuCP, usually either to SET some value into a H/W periphery or
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* to GET the current value of some H/W periphery. For example, SET the
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* frequency of MME/TPC and GET the value of the thermal sensor.
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*
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* These messages can be initiated either by the User application or by the
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* host's driver itself, e.g. power management code. In either case, the
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* communication from the host's driver to CpuCP will *always* be in
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* synchronous mode, meaning that the host will send a single message and poll
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* until the message was acknowledged and the results are ready (if results are
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* needed).
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*
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* This means that only a single message can be sent at a time and the host's
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* driver must wait for its result before sending the next message. Having said
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* that, because these are control messages which are sent in a relatively low
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* frequency, this limitation seems acceptable. It's important to note that
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* in case of multiple devices, messages to different devices *can* be sent
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* at the same time.
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*
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* The message, inputs/outputs (if relevant) and fence object will be located
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* on the device DDR at an address that will be determined by the host's driver.
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* During device initialization phase, the host will pass to CpuCP that address.
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* Most of the message types will contain inputs/outputs inside the message
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* itself. The common part of each message will contain the opcode of the
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* message (its type) and a field representing a fence object.
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*
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* When the host's driver wishes to send a message to CPU CP, it will write the
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* message contents to the device DDR, clear the fence object and then write to
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* the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU.
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*
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* Upon receiving the interrupt (#121), CpuCP will read the message from the
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* DDR. In case the message is a SET operation, CpuCP will first perform the
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* operation and then write to the fence object on the device DDR. In case the
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* message is a GET operation, CpuCP will first fill the results section on the
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* device DDR and then write to the fence object. If an error occurred, CpuCP
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* will fill the rc field with the right error code.
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*
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* In the meantime, the host's driver will poll on the fence object. Once the
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* host sees that the fence object is signaled, it will read the results from
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* the device DDR (if relevant) and resume the code execution in the host's
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* driver.
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*
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* To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8
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* so the value being put by the host's driver matches the value read by CpuCP
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*
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* Non-QMAN packets should be limited to values 1 through (2^8 - 1)
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*
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* Detailed description:
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*
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* CPUCP_PACKET_DISABLE_PCI_ACCESS -
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* After receiving this packet the embedded CPU must NOT issue PCI
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* transactions (read/write) towards the Host CPU. This also include
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* sending MSI-X interrupts.
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* This packet is usually sent before the device is moved to D3Hot state.
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*
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* CPUCP_PACKET_ENABLE_PCI_ACCESS -
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* After receiving this packet the embedded CPU is allowed to issue PCI
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* transactions towards the Host CPU, including sending MSI-X interrupts.
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* This packet is usually send after the device is moved to D0 state.
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*
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* CPUCP_PACKET_TEMPERATURE_GET -
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* Fetch the current temperature / Max / Max Hyst / Critical /
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* Critical Hyst of a specified thermal sensor. The packet's
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* arguments specify the desired sensor and the field to get.
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*
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* CPUCP_PACKET_VOLTAGE_GET -
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* Fetch the voltage / Max / Min of a specified sensor. The packet's
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* arguments specify the sensor and type.
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*
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* CPUCP_PACKET_CURRENT_GET -
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* Fetch the current / Max / Min of a specified sensor. The packet's
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* arguments specify the sensor and type.
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*
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* CPUCP_PACKET_FAN_SPEED_GET -
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* Fetch the speed / Max / Min of a specified fan. The packet's
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* arguments specify the sensor and type.
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*
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* CPUCP_PACKET_PWM_GET -
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* Fetch the pwm value / mode of a specified pwm. The packet's
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* arguments specify the sensor and type.
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*
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* CPUCP_PACKET_PWM_SET -
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* Set the pwm value / mode of a specified pwm. The packet's
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* arguments specify the sensor, type and value.
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*
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* CPUCP_PACKET_FREQUENCY_SET -
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* Set the frequency of a specified PLL. The packet's arguments specify
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* the PLL and the desired frequency. The actual frequency in the device
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* might differ from the requested frequency.
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*
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* CPUCP_PACKET_FREQUENCY_GET -
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* Fetch the frequency of a specified PLL. The packet's arguments specify
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* the PLL.
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*
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* CPUCP_PACKET_LED_SET -
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* Set the state of a specified led. The packet's arguments
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* specify the led and the desired state.
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*
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* CPUCP_PACKET_I2C_WR -
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* Write 32-bit value to I2C device. The packet's arguments specify the
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* I2C bus, address and value.
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*
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* CPUCP_PACKET_I2C_RD -
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* Read 32-bit value from I2C device. The packet's arguments specify the
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* I2C bus and address.
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*
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* CPUCP_PACKET_INFO_GET -
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* Fetch information from the device as specified in the packet's
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* structure. The host's driver passes the max size it allows the CpuCP to
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* write to the structure, to prevent data corruption in case of
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* mismatched driver/FW versions.
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*
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* CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed
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*
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* CPUCP_PACKET_UNMASK_RAZWI_IRQ -
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* Unmask the given IRQ. The IRQ number is specified in the value field.
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* The packet is sent after receiving an interrupt and printing its
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* relevant information.
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*
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* CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY -
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* Unmask the given IRQs. The IRQs numbers are specified in an array right
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* after the cpucp_packet structure, where its first element is the array
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* length. The packet is sent after a soft reset was done in order to
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* handle any interrupts that were sent during the reset process.
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*
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* CPUCP_PACKET_TEST -
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* Test packet for CpuCP connectivity. The CPU will put the fence value
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* in the result field.
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*
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* CPUCP_PACKET_FREQUENCY_CURR_GET -
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* Fetch the current frequency of a specified PLL. The packet's arguments
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* specify the PLL.
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*
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* CPUCP_PACKET_MAX_POWER_GET -
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* Fetch the maximal power of the device.
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*
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* CPUCP_PACKET_MAX_POWER_SET -
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* Set the maximal power of the device. The packet's arguments specify
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* the power.
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*
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* CPUCP_PACKET_EEPROM_DATA_GET -
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* Get EEPROM data from the CpuCP kernel. The buffer is specified in the
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* addr field. The CPU will put the returned data size in the result
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* field. In addition, the host's driver passes the max size it allows the
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* CpuCP to write to the structure, to prevent data corruption in case of
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* mismatched driver/FW versions.
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*
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* CPUCP_PACKET_NIC_INFO_GET -
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* Fetch information from the device regarding the NIC. the host's driver
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* passes the max size it allows the CpuCP to write to the structure, to
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* prevent data corruption in case of mismatched driver/FW versions.
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*
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* CPUCP_PACKET_TEMPERATURE_SET -
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* Set the value of the offset property of a specified thermal sensor.
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* The packet's arguments specify the desired sensor and the field to
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* set.
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*
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* CPUCP_PACKET_VOLTAGE_SET -
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* Trigger the reset_history property of a specified voltage sensor.
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* The packet's arguments specify the desired sensor and the field to
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* set.
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*
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* CPUCP_PACKET_CURRENT_SET -
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* Trigger the reset_history property of a specified current sensor.
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* The packet's arguments specify the desired sensor and the field to
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* set.
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*
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* CPUCP_PACKET_PCIE_THROUGHPUT_GET
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* Get throughput of PCIe.
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* The packet's arguments specify the transaction direction (TX/RX).
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* The window measurement is 10[msec], and the return value is in KB/sec.
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*
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* CPUCP_PACKET_PCIE_REPLAY_CNT_GET
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* Replay count measures number of "replay" events, which is basicly
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* number of retries done by PCIe.
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*
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* CPUCP_PACKET_TOTAL_ENERGY_GET
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* Total Energy is measurement of energy from the time FW Linux
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* is loaded. It is calculated by multiplying the average power
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* by time (passed from armcp start). The units are in MilliJouls.
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*
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* CPUCP_PACKET_PLL_INFO_GET
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* Fetch frequencies of PLL from the required PLL IP.
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* The packet's arguments specify the device PLL type
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* Pll type is the PLL from device pll_index enum.
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* The result is composed of 4 outputs, each is 16-bit
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* frequency in MHz.
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*
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* CPUCP_PACKET_POWER_GET
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* Fetch the present power consumption of the device (Current * Voltage).
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*
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*/
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enum cpucp_packet_id {
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CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */
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CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */
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CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */
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CPUCP_PACKET_VOLTAGE_GET, /* sysfs */
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CPUCP_PACKET_CURRENT_GET, /* sysfs */
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CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */
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CPUCP_PACKET_PWM_GET, /* sysfs */
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CPUCP_PACKET_PWM_SET, /* sysfs */
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CPUCP_PACKET_FREQUENCY_SET, /* sysfs */
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CPUCP_PACKET_FREQUENCY_GET, /* sysfs */
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CPUCP_PACKET_LED_SET, /* debugfs */
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CPUCP_PACKET_I2C_WR, /* debugfs */
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CPUCP_PACKET_I2C_RD, /* debugfs */
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CPUCP_PACKET_INFO_GET, /* IOCTL */
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CPUCP_PACKET_FLASH_PROGRAM_REMOVED,
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CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */
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CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */
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CPUCP_PACKET_TEST, /* internal */
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CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */
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CPUCP_PACKET_MAX_POWER_GET, /* sysfs */
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CPUCP_PACKET_MAX_POWER_SET, /* sysfs */
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CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */
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CPUCP_PACKET_NIC_INFO_GET, /* internal */
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CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */
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CPUCP_PACKET_VOLTAGE_SET, /* sysfs */
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CPUCP_PACKET_CURRENT_SET, /* sysfs */
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CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */
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CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */
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CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */
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CPUCP_PACKET_PLL_INFO_GET, /* internal */
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CPUCP_PACKET_NIC_STATUS, /* internal */
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CPUCP_PACKET_POWER_GET, /* internal */
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};
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#define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5
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#define CPUCP_PKT_CTL_RC_SHIFT 12
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#define CPUCP_PKT_CTL_RC_MASK 0x0000F000
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#define CPUCP_PKT_CTL_OPCODE_SHIFT 16
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#define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000
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#define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0
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#define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull
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#define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16
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#define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull
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#define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32
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#define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull
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#define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48
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#define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull
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struct cpucp_packet {
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union {
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__le64 value; /* For SET packets */
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__le64 result; /* For GET packets */
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__le64 addr; /* For PQ */
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};
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__le32 ctl;
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__le32 fence; /* Signal to host that message is completed */
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union {
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struct {/* For temperature/current/voltage/fan/pwm get/set */
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__le16 sensor_index;
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__le16 type;
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};
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struct { /* For I2C read/write */
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__u8 i2c_bus;
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__u8 i2c_addr;
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__u8 i2c_reg;
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__u8 pad; /* unused */
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};
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struct {/* For PLL info fetch */
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__le16 pll_type;
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/* TODO pll_reg is kept temporary before removal */
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__le16 pll_reg;
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};
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/* For any general request */
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__le32 index;
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/* For frequency get/set */
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__le32 pll_index;
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/* For led set */
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__le32 led_index;
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/* For get CpuCP info/EEPROM data/NIC info */
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__le32 data_max_size;
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};
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__le32 reserved;
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};
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struct cpucp_unmask_irq_arr_packet {
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struct cpucp_packet cpucp_pkt;
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__le32 length;
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__le32 irqs[0];
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};
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enum cpucp_packet_rc {
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cpucp_packet_success,
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cpucp_packet_invalid,
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cpucp_packet_fault
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};
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/*
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* cpucp_temp_type should adhere to hwmon_temp_attributes
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* defined in Linux kernel hwmon.h file
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*/
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enum cpucp_temp_type {
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cpucp_temp_input,
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cpucp_temp_max = 6,
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cpucp_temp_max_hyst,
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cpucp_temp_crit,
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cpucp_temp_crit_hyst,
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cpucp_temp_offset = 19,
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cpucp_temp_highest = 22,
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cpucp_temp_reset_history = 23
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};
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enum cpucp_in_attributes {
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cpucp_in_input,
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cpucp_in_min,
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cpucp_in_max,
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cpucp_in_highest = 7,
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cpucp_in_reset_history
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};
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enum cpucp_curr_attributes {
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cpucp_curr_input,
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cpucp_curr_min,
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cpucp_curr_max,
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cpucp_curr_highest = 7,
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cpucp_curr_reset_history
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};
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enum cpucp_fan_attributes {
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cpucp_fan_input,
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cpucp_fan_min = 2,
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cpucp_fan_max
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};
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enum cpucp_pwm_attributes {
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cpucp_pwm_input,
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cpucp_pwm_enable
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};
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enum cpucp_pcie_throughput_attributes {
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cpucp_pcie_throughput_tx,
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cpucp_pcie_throughput_rx
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};
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/* TODO temporary kept before removal */
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enum cpucp_pll_reg_attributes {
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cpucp_pll_nr_reg,
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cpucp_pll_nf_reg,
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cpucp_pll_od_reg,
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|
cpucp_pll_div_factor_reg,
|
|
cpucp_pll_div_sel_reg
|
|
};
|
|
|
|
/* TODO temporary kept before removal */
|
|
enum cpucp_pll_type_attributes {
|
|
cpucp_pll_cpu,
|
|
cpucp_pll_pci,
|
|
};
|
|
|
|
/* Event Queue Packets */
|
|
|
|
struct eq_generic_event {
|
|
__le64 data[7];
|
|
};
|
|
|
|
/*
|
|
* CpuCP info
|
|
*/
|
|
|
|
#define CARD_NAME_MAX_LEN 16
|
|
#define VERSION_MAX_LEN 128
|
|
#define CPUCP_MAX_SENSORS 128
|
|
#define CPUCP_MAX_NICS 128
|
|
#define CPUCP_LANES_PER_NIC 4
|
|
#define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024
|
|
#define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC)
|
|
#define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64)
|
|
#define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64)
|
|
|
|
struct cpucp_sensor {
|
|
__le32 type;
|
|
__le32 flags;
|
|
};
|
|
|
|
/**
|
|
* struct cpucp_card_types - ASIC card type.
|
|
* @cpucp_card_type_pci: PCI card.
|
|
* @cpucp_card_type_pmc: PCI Mezzanine Card.
|
|
*/
|
|
enum cpucp_card_types {
|
|
cpucp_card_type_pci,
|
|
cpucp_card_type_pmc
|
|
};
|
|
|
|
#define CPUCP_SEC_CONF_ENABLED_SHIFT 0
|
|
#define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001
|
|
|
|
#define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1
|
|
#define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002
|
|
|
|
#define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2
|
|
#define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004
|
|
|
|
/**
|
|
* struct cpucp_security_info - Security information.
|
|
* @config: configuration bit field
|
|
* @keys_num: number of stored keys
|
|
* @revoked_keys: revoked keys bit field
|
|
* @min_svn: minimal security version
|
|
*/
|
|
struct cpucp_security_info {
|
|
__u8 config;
|
|
__u8 keys_num;
|
|
__u8 revoked_keys;
|
|
__u8 min_svn;
|
|
};
|
|
|
|
/**
|
|
* struct cpucp_info - Info from CpuCP that is necessary to the host's driver
|
|
* @sensors: available sensors description.
|
|
* @kernel_version: CpuCP linux kernel version.
|
|
* @reserved: reserved field.
|
|
* @card_type: card configuration type.
|
|
* @card_location: in a server, each card has different connections topology
|
|
* depending on its location (relevant for PMC card type)
|
|
* @cpld_version: CPLD programmed F/W version.
|
|
* @infineon_version: Infineon main DC-DC version.
|
|
* @fuse_version: silicon production FUSE information.
|
|
* @thermal_version: thermald S/W version.
|
|
* @cpucp_version: CpuCP S/W version.
|
|
* @dram_size: available DRAM size.
|
|
* @card_name: card name that will be displayed in HWMON subsystem on the host
|
|
* @sec_info: security information
|
|
*/
|
|
struct cpucp_info {
|
|
struct cpucp_sensor sensors[CPUCP_MAX_SENSORS];
|
|
__u8 kernel_version[VERSION_MAX_LEN];
|
|
__le32 reserved;
|
|
__le32 card_type;
|
|
__le32 card_location;
|
|
__le32 cpld_version;
|
|
__le32 infineon_version;
|
|
__u8 fuse_version[VERSION_MAX_LEN];
|
|
__u8 thermal_version[VERSION_MAX_LEN];
|
|
__u8 cpucp_version[VERSION_MAX_LEN];
|
|
__le32 reserved2;
|
|
__le64 dram_size;
|
|
char card_name[CARD_NAME_MAX_LEN];
|
|
__le64 reserved3;
|
|
__le64 reserved4;
|
|
__u8 reserved5;
|
|
__u8 pad[7];
|
|
struct cpucp_security_info sec_info;
|
|
__le32 reserved6;
|
|
};
|
|
|
|
struct cpucp_mac_addr {
|
|
__u8 mac_addr[ETH_ALEN];
|
|
};
|
|
|
|
struct cpucp_nic_info {
|
|
struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS];
|
|
__le64 link_mask[CPUCP_NIC_MASK_ARR_LEN];
|
|
__le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
|
|
__le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
|
|
__le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN];
|
|
__u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN];
|
|
__le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN];
|
|
};
|
|
|
|
#endif /* CPUCP_IF_H */
|