290 lines
6.7 KiB
C
290 lines
6.7 KiB
C
/*
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* Special handling for DW core on Intel MID platform
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*
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* Copyright (c) 2009, 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#include "spi-dw.h"
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#ifdef CONFIG_SPI_DW_MID_DMA
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#include <linux/intel_mid_dma.h>
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#include <linux/pci.h>
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#define RX_BUSY 0
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#define TX_BUSY 1
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struct mid_dma {
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struct intel_mid_dma_slave dmas_tx;
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struct intel_mid_dma_slave dmas_rx;
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};
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static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
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{
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struct dw_spi *dws = param;
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return dws->dma_dev == chan->device->dev;
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}
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static int mid_spi_dma_init(struct dw_spi *dws)
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{
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struct mid_dma *dw_dma = dws->dma_priv;
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struct pci_dev *dma_dev;
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struct intel_mid_dma_slave *rxs, *txs;
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dma_cap_mask_t mask;
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/*
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* Get pci device for DMA controller, currently it could only
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* be the DMA controller of Medfield
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*/
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dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
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if (!dma_dev)
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return -ENODEV;
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dws->dma_dev = &dma_dev->dev;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/* 1. Init rx channel */
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dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
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if (!dws->rxchan)
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goto err_exit;
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rxs = &dw_dma->dmas_rx;
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rxs->hs_mode = LNW_DMA_HW_HS;
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rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
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dws->rxchan->private = rxs;
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/* 2. Init tx channel */
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dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
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if (!dws->txchan)
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goto free_rxchan;
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txs = &dw_dma->dmas_tx;
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txs->hs_mode = LNW_DMA_HW_HS;
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txs->cfg_mode = LNW_DMA_MEM_TO_PER;
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dws->txchan->private = txs;
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dws->dma_inited = 1;
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return 0;
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free_rxchan:
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dma_release_channel(dws->rxchan);
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err_exit:
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return -EBUSY;
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}
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static void mid_spi_dma_exit(struct dw_spi *dws)
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{
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if (!dws->dma_inited)
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return;
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dmaengine_terminate_all(dws->txchan);
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dma_release_channel(dws->txchan);
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dmaengine_terminate_all(dws->rxchan);
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dma_release_channel(dws->rxchan);
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}
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/*
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* dws->dma_chan_busy is set before the dma transfer starts, callback for tx
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* channel will clear a corresponding bit.
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*/
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static void dw_spi_dma_tx_done(void *arg)
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{
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struct dw_spi *dws = arg;
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if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY))
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return;
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dw_spi_xfer_done(dws);
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}
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
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{
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struct dma_slave_config txconf;
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struct dma_async_tx_descriptor *txdesc;
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if (!dws->tx_dma)
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return NULL;
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txconf.direction = DMA_MEM_TO_DEV;
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txconf.dst_addr = dws->dma_addr;
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txconf.dst_maxburst = LNW_DMA_MSIZE_16;
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txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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txconf.dst_addr_width = dws->dma_width;
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txconf.device_fc = false;
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dmaengine_slave_config(dws->txchan, &txconf);
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memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
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dws->tx_sgl.dma_address = dws->tx_dma;
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dws->tx_sgl.length = dws->len;
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txdesc = dmaengine_prep_slave_sg(dws->txchan,
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&dws->tx_sgl,
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1,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!txdesc)
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return NULL;
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txdesc->callback = dw_spi_dma_tx_done;
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txdesc->callback_param = dws;
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return txdesc;
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}
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/*
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* dws->dma_chan_busy is set before the dma transfer starts, callback for rx
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* channel will clear a corresponding bit.
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*/
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static void dw_spi_dma_rx_done(void *arg)
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{
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struct dw_spi *dws = arg;
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if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY))
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return;
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dw_spi_xfer_done(dws);
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}
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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{
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struct dma_slave_config rxconf;
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struct dma_async_tx_descriptor *rxdesc;
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if (!dws->rx_dma)
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return NULL;
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rxconf.direction = DMA_DEV_TO_MEM;
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rxconf.src_addr = dws->dma_addr;
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rxconf.src_maxburst = LNW_DMA_MSIZE_16;
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rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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rxconf.src_addr_width = dws->dma_width;
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rxconf.device_fc = false;
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dmaengine_slave_config(dws->rxchan, &rxconf);
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memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
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dws->rx_sgl.dma_address = dws->rx_dma;
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dws->rx_sgl.length = dws->len;
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rxdesc = dmaengine_prep_slave_sg(dws->rxchan,
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&dws->rx_sgl,
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1,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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if (!rxdesc)
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return NULL;
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rxdesc->callback = dw_spi_dma_rx_done;
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rxdesc->callback_param = dws;
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return rxdesc;
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}
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static void dw_spi_dma_setup(struct dw_spi *dws)
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{
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u16 dma_ctrl = 0;
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spi_enable_chip(dws, 0);
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dw_writew(dws, DW_SPI_DMARDLR, 0xf);
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dw_writew(dws, DW_SPI_DMATDLR, 0x10);
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if (dws->tx_dma)
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dma_ctrl |= SPI_DMA_TDMAE;
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if (dws->rx_dma)
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dma_ctrl |= SPI_DMA_RDMAE;
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dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
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spi_enable_chip(dws, 1);
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}
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static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
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{
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struct dma_async_tx_descriptor *txdesc, *rxdesc;
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/* 1. setup DMA related registers */
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if (cs_change)
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dw_spi_dma_setup(dws);
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/* 2. Prepare the TX dma transfer */
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txdesc = dw_spi_dma_prepare_tx(dws);
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/* 3. Prepare the RX dma transfer */
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rxdesc = dw_spi_dma_prepare_rx(dws);
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/* rx must be started before tx due to spi instinct */
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if (rxdesc) {
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set_bit(RX_BUSY, &dws->dma_chan_busy);
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dmaengine_submit(rxdesc);
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dma_async_issue_pending(dws->rxchan);
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}
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if (txdesc) {
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set_bit(TX_BUSY, &dws->dma_chan_busy);
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dmaengine_submit(txdesc);
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dma_async_issue_pending(dws->txchan);
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}
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return 0;
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}
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static struct dw_spi_dma_ops mid_dma_ops = {
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.dma_init = mid_spi_dma_init,
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.dma_exit = mid_spi_dma_exit,
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.dma_transfer = mid_spi_dma_transfer,
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};
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#endif
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/* Some specific info for SPI0 controller on Intel MID */
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/* HW info for MRST Clk Control Unit, 32b reg per controller */
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#define MRST_SPI_CLK_BASE 100000000 /* 100m */
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#define MRST_CLK_SPI_REG 0xff11d86c
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#define CLK_SPI_BDIV_OFFSET 0
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#define CLK_SPI_BDIV_MASK 0x00000007
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#define CLK_SPI_CDIV_OFFSET 9
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#define CLK_SPI_CDIV_MASK 0x00000e00
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#define CLK_SPI_DISABLE_OFFSET 8
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int dw_spi_mid_init(struct dw_spi *dws)
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{
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void __iomem *clk_reg;
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u32 clk_cdiv;
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clk_reg = ioremap_nocache(MRST_CLK_SPI_REG, 16);
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if (!clk_reg)
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return -ENOMEM;
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/* Get SPI controller operating freq info */
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clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
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clk_cdiv &= CLK_SPI_CDIV_MASK;
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clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
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dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
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iounmap(clk_reg);
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#ifdef CONFIG_SPI_DW_MID_DMA
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dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
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if (!dws->dma_priv)
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return -ENOMEM;
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dws->dma_ops = &mid_dma_ops;
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#endif
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return 0;
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}
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