391 lines
10 KiB
C
391 lines
10 KiB
C
/*
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* AM33XX PRM functions
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "powerdomain.h"
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#include "prm33xx.h"
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#include "prm-regbits-33xx.h"
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#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000
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#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
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/* Read a register in a PRM instance */
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static u32 am33xx_prm_read_reg(s16 inst, u16 idx)
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{
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return readl_relaxed(prm_base + inst + idx);
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}
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/* Write into a register in a PRM instance */
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static void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
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{
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writel_relaxed(val, prm_base + inst + idx);
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}
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/* Read-modify-write a register in PRM. Caller must lock */
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static u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
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{
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u32 v;
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v = am33xx_prm_read_reg(inst, idx);
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v &= ~mask;
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v |= bits;
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am33xx_prm_write_reg(v, inst, idx);
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return v;
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}
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/**
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* am33xx_prm_is_hardreset_asserted - read the HW reset line state of
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* submodules contained in the hwmod module
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* @shift: register bit shift corresponding to the reset line to check
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* @part: PRM partition, ignored for AM33xx
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* @inst: CM instance register offset (*_INST macro)
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* @rstctrl_offs: RM_RSTCTRL register address offset for this module
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*
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* Returns 1 if the (sub)module hardreset line is currently asserted,
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* 0 if the (sub)module hardreset line is not currently asserted, or
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* -EINVAL upon parameter error.
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*/
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static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
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u16 rstctrl_offs)
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{
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u32 v;
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v = am33xx_prm_read_reg(inst, rstctrl_offs);
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v &= 1 << shift;
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v >>= shift;
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return v;
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}
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/**
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* am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
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* @shift: register bit shift corresponding to the reset line to assert
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* @part: CM partition, ignored for AM33xx
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* @inst: CM instance register offset (*_INST macro)
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* place the submodule into reset. Returns 0 upon success or -EINVAL
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* upon an argument error.
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*/
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static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst,
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u16 rstctrl_offs)
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{
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u32 mask = 1 << shift;
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am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
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return 0;
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}
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/**
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* am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
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* wait
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* @shift: register bit shift corresponding to the reset line to deassert
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* @st_shift: reset status register bit shift corresponding to the reset line
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* @part: PRM partition, not used for AM33xx
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* @inst: CM instance register offset (*_INST macro)
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* @rstctrl_reg: RM_RSTCTRL register address for this module
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* @rstst_reg: RM_RSTST register address for this module
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*
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* Some IPs like dsp, ipu or iva contain processors that require an HW
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* reset line to be asserted / deasserted in order to fully enable the
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* IP. These modules may have multiple hard-reset lines that reset
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* different 'submodules' inside the IP block. This function will
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* take the submodule out of reset and wait until the PRCM indicates
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* that the reset has completed before returning. Returns 0 upon success or
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* -EINVAL upon an argument error, -EEXIST if the submodule was already out
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* of reset, or -EBUSY if the submodule did not exit reset promptly.
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*/
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static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
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s16 inst, u16 rstctrl_offs,
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u16 rstst_offs)
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{
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int c;
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u32 mask = 1 << st_shift;
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/* Check the current status to avoid de-asserting the line twice */
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if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0)
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return -EEXIST;
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/* Clear the reset status by writing 1 to the status bit */
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am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
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/* de-assert the reset control line */
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mask = 1 << shift;
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am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
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/* wait the status to be set */
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omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst,
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rstst_offs),
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MAX_MODULE_HARDRESET_WAIT, c);
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return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
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}
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static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
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{
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am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
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(pwrst << OMAP_POWERSTATE_SHIFT),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
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{
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u32 v;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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v &= OMAP_POWERSTATE_MASK;
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v >>= OMAP_POWERSTATE_SHIFT;
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return v;
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}
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static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
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{
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u32 v;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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v &= OMAP_POWERSTATEST_MASK;
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v >>= OMAP_POWERSTATEST_SHIFT;
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return v;
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}
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static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
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{
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u32 v;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
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v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
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return v;
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}
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static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
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{
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am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
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(1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
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{
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am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
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AM33XX_LASTPOWERSTATEENTERED_MASK,
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pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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return 0;
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}
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static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
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{
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u32 m;
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m = pwrdm->logicretstate_mask;
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if (!m)
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return -EINVAL;
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am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
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{
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u32 v;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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v &= AM33XX_LOGICSTATEST_MASK;
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v >>= AM33XX_LOGICSTATEST_SHIFT;
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return v;
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}
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static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
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{
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u32 v, m;
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m = pwrdm->logicretstate_mask;
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if (!m)
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return -EINVAL;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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v &= m;
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v >>= __ffs(m);
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return v;
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}
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static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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{
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u32 m;
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m = pwrdm->mem_on_mask[bank];
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if (!m)
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return -EINVAL;
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am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
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u8 pwrst)
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{
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u32 m;
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m = pwrdm->mem_ret_mask[bank];
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if (!m)
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return -EINVAL;
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am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
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pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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return 0;
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}
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static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m, v;
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m = pwrdm->mem_pwrst_mask[bank];
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if (!m)
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return -EINVAL;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
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v &= m;
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v >>= __ffs(m);
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return v;
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}
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static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
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{
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u32 m, v;
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m = pwrdm->mem_retst_mask[bank];
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if (!m)
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return -EINVAL;
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v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
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v &= m;
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v >>= __ffs(m);
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return v;
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}
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static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
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{
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u32 c = 0;
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/*
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* REVISIT: pwrdm_wait_transition() may be better implemented
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* via a callback and a periodic timer check -- how long do we expect
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* powerdomain transitions to take?
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*/
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/* XXX Is this udelay() value meaningful? */
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while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
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& OMAP_INTRANSITION_MASK) &&
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(c++ < PWRDM_TRANSITION_BAILOUT))
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udelay(1);
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if (c > PWRDM_TRANSITION_BAILOUT) {
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pr_err("powerdomain: %s: waited too long to complete transition\n",
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pwrdm->name);
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return -EAGAIN;
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}
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pr_debug("powerdomain: completed transition in %d loops\n", c);
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return 0;
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}
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static int am33xx_check_vcvp(void)
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{
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/* No VC/VP on am33xx devices */
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return 0;
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}
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/**
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* am33xx_prm_global_warm_sw_reset - reboot the device via warm reset
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*
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* Immediately reboots the device through warm reset.
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*/
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static void am33xx_prm_global_warm_sw_reset(void)
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{
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am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK,
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AM33XX_RST_GLOBAL_WARM_SW_MASK,
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AM33XX_PRM_DEVICE_MOD,
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AM33XX_PRM_RSTCTRL_OFFSET);
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/* OCP barrier */
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(void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
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AM33XX_PRM_RSTCTRL_OFFSET);
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}
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struct pwrdm_ops am33xx_pwrdm_operations = {
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.pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
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.pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
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.pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
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.pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
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.pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
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.pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
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.pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
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.pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
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.pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
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.pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
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.pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
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.pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
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.pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
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.pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
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.pwrdm_has_voltdm = am33xx_check_vcvp,
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};
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static struct prm_ll_data am33xx_prm_ll_data = {
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.assert_hardreset = am33xx_prm_assert_hardreset,
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.deassert_hardreset = am33xx_prm_deassert_hardreset,
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.is_hardreset_asserted = am33xx_prm_is_hardreset_asserted,
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.reset_system = am33xx_prm_global_warm_sw_reset,
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};
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int __init am33xx_prm_init(const struct omap_prcm_init_data *data)
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{
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return prm_register(&am33xx_prm_ll_data);
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}
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static void __exit am33xx_prm_exit(void)
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{
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prm_unregister(&am33xx_prm_ll_data);
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}
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__exitcall(am33xx_prm_exit);
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