178 lines
3.9 KiB
C
178 lines
3.9 KiB
C
/*
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* linux/arch/arm/kernel/xscale-cp0.c
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*
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* XScale DSP and iWMMXt coprocessor context switching and handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/thread_notify.h>
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static inline void dsp_save_state(u32 *state)
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{
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__asm__ __volatile__ (
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"mrrc p0, 0, %0, %1, c0\n"
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: "=r" (state[0]), "=r" (state[1]));
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}
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static inline void dsp_load_state(u32 *state)
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{
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__asm__ __volatile__ (
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"mcrr p0, 0, %0, %1, c0\n"
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: : "r" (state[0]), "r" (state[1]));
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}
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static int dsp_do(struct notifier_block *self, unsigned long cmd, void *t)
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{
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struct thread_info *thread = t;
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switch (cmd) {
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case THREAD_NOTIFY_FLUSH:
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thread->cpu_context.extra[0] = 0;
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thread->cpu_context.extra[1] = 0;
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break;
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case THREAD_NOTIFY_SWITCH:
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dsp_save_state(current_thread_info()->cpu_context.extra);
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dsp_load_state(thread->cpu_context.extra);
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break;
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}
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return NOTIFY_DONE;
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}
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static struct notifier_block dsp_notifier_block = {
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.notifier_call = dsp_do,
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};
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#ifdef CONFIG_IWMMXT
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static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
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{
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struct thread_info *thread = t;
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switch (cmd) {
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case THREAD_NOTIFY_FLUSH:
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/*
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* flush_thread() zeroes thread->fpstate, so no need
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* to do anything here.
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*
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* FALLTHROUGH: Ensure we don't try to overwrite our newly
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* initialised state information on the first fault.
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*/
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case THREAD_NOTIFY_EXIT:
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iwmmxt_task_release(thread);
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break;
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case THREAD_NOTIFY_SWITCH:
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iwmmxt_task_switch(thread);
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break;
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}
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return NOTIFY_DONE;
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}
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static struct notifier_block iwmmxt_notifier_block = {
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.notifier_call = iwmmxt_do,
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};
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#endif
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static u32 __init xscale_cp_access_read(void)
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{
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u32 value;
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__asm__ __volatile__ (
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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: "=r" (value));
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return value;
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}
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static void __init xscale_cp_access_write(u32 value)
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{
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u32 temp;
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__asm__ __volatile__ (
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"mcr p15, 0, %1, c15, c1, 0\n\t"
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4\n\t"
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: "=r" (temp) : "r" (value));
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}
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/*
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* Detect whether we have a MAC coprocessor (40 bit register) or an
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* iWMMXt coprocessor (64 bit registers) by loading 00000100:00000000
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* into a coprocessor register and reading it back, and checking
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* whether the upper word survived intact.
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*/
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static int __init cpu_has_iwmmxt(void)
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{
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u32 lo;
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u32 hi;
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/*
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* This sequence is interpreted by the DSP coprocessor as:
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* mar acc0, %2, %3
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* mra %0, %1, acc0
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*
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* And by the iWMMXt coprocessor as:
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* tmcrr wR0, %2, %3
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* tmrrc %0, %1, wR0
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*/
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__asm__ __volatile__ (
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"mcrr p0, 0, %2, %3, c0\n"
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"mrrc p0, 0, %0, %1, c0\n"
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: "=r" (lo), "=r" (hi)
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: "r" (0), "r" (0x100));
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return !!hi;
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}
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/*
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* If we detect that the CPU has iWMMXt (and CONFIG_IWMMXT=y), we
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* disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
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* switch code handle iWMMXt context switching. If on the other
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* hand the CPU has a DSP coprocessor, we keep access to CP0 enabled
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* all the time, and save/restore acc0 on context switch in non-lazy
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* fashion.
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*/
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static int __init xscale_cp0_init(void)
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{
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u32 cp_access;
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cp_access = xscale_cp_access_read() & ~3;
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xscale_cp_access_write(cp_access | 1);
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if (cpu_has_iwmmxt()) {
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#ifndef CONFIG_IWMMXT
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pr_warn("CAUTION: XScale iWMMXt coprocessor detected, but kernel support is missing.\n");
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#else
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pr_info("XScale iWMMXt coprocessor detected.\n");
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elf_hwcap |= HWCAP_IWMMXT;
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thread_register_notifier(&iwmmxt_notifier_block);
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#endif
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} else {
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pr_info("XScale DSP coprocessor detected.\n");
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thread_register_notifier(&dsp_notifier_block);
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cp_access |= 1;
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}
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xscale_cp_access_write(cp_access);
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return 0;
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}
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late_initcall(xscale_cp0_init);
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