302 lines
7.1 KiB
C
302 lines
7.1 KiB
C
/* soc.h: Definitions for Sparc SUNW,soc Fibre Channel Sbus driver.
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*
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* Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#ifndef __SOC_H
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#define __SOC_H
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#include "fc.h"
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#include "fcp.h"
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#include "fcp_impl.h"
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/* Hardware register offsets and constants first {{{ */
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#define CFG 0x00UL /* Config Register */
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#define SAE 0x04UL /* Slave Access Error Register */
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#define CMD 0x08UL /* Command and Status Register */
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#define IMASK 0x0cUL /* Interrupt Mask Register */
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/* Config Register */
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#define SOC_CFG_EXT_RAM_BANK_MASK 0x07000000
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#define SOC_CFG_EEPROM_BANK_MASK 0x00030000
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#define SOC_CFG_BURST64_MASK 0x00000700
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#define SOC_CFG_SBUS_PARITY_TEST 0x00000020
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#define SOC_CFG_SBUS_PARITY_CHECK 0x00000010
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#define SOC_CFG_SBUS_ENHANCED 0x00000008
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#define SOC_CFG_BURST_MASK 0x00000007
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/* Bursts */
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#define SOC_CFG_BURST_4 0x00000000
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#define SOC_CFG_BURST_16 0x00000004
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#define SOC_CFG_BURST_32 0x00000005
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#define SOC_CFG_BURST_64 0x00000006
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/* Slave Access Error Register */
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#define SOC_SAE_ALIGNMENT 0x00000004
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#define SOC_SAE_UNSUPPORTED 0x00000002
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#define SOC_SAE_PARITY 0x00000001
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/* Command & Status Register */
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#define SOC_CMD_RSP_QALL 0x000f0000
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#define SOC_CMD_RSP_Q0 0x00010000
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#define SOC_CMD_RSP_Q1 0x00020000
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#define SOC_CMD_RSP_Q2 0x00040000
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#define SOC_CMD_RSP_Q3 0x00080000
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#define SOC_CMD_REQ_QALL 0x00000f00
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#define SOC_CMD_REQ_Q0 0x00000100
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#define SOC_CMD_REQ_Q1 0x00000200
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#define SOC_CMD_REQ_Q2 0x00000400
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#define SOC_CMD_REQ_Q3 0x00000800
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#define SOC_CMD_SAE 0x00000080
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#define SOC_CMD_INTR_PENDING 0x00000008
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#define SOC_CMD_NON_QUEUED 0x00000004
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#define SOC_CMD_IDLE 0x00000002
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#define SOC_CMD_SOFT_RESET 0x00000001
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/* Interrupt Mask Register */
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#define SOC_IMASK_RSP_QALL 0x000f0000
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#define SOC_IMASK_RSP_Q0 0x00010000
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#define SOC_IMASK_RSP_Q1 0x00020000
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#define SOC_IMASK_RSP_Q2 0x00040000
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#define SOC_IMASK_RSP_Q3 0x00080000
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#define SOC_IMASK_REQ_QALL 0x00000f00
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#define SOC_IMASK_REQ_Q0 0x00000100
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#define SOC_IMASK_REQ_Q1 0x00000200
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#define SOC_IMASK_REQ_Q2 0x00000400
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#define SOC_IMASK_REQ_Q3 0x00000800
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#define SOC_IMASK_SAE 0x00000080
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#define SOC_IMASK_NON_QUEUED 0x00000004
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#define SOC_INTR(s, cmd) \
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(((cmd & SOC_CMD_RSP_QALL) | ((~cmd) & SOC_CMD_REQ_QALL)) \
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& s->imask)
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#define SOC_SETIMASK(s, i) \
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do { (s)->imask = (i); \
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sbus_writel((i), (s)->regs + IMASK); \
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} while(0)
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/* XRAM
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*
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* This is a 64KB register area. It accepts only halfword access.
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* That's why here are the following inline functions...
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*/
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typedef void __iomem *xram_p;
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/* Get 32bit number from XRAM */
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static inline u32 xram_get_32(xram_p x)
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{
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return ((sbus_readw(x + 0x00UL) << 16) |
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(sbus_readw(x + 0x02UL)));
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}
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/* Like the above, but when we don't care about the high 16 bits */
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static inline u32 xram_get_32low(xram_p x)
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{
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return (u32) sbus_readw(x + 0x02UL);
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}
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static inline u16 xram_get_16(xram_p x)
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{
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return sbus_readw(x);
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}
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static inline u8 xram_get_8(xram_p x)
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{
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if ((unsigned long)x & 0x1UL) {
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x = x - 1;
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return (u8) sbus_readw(x);
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} else {
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return (u8) (sbus_readw(x) >> 8);
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}
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}
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static inline void xram_copy_from(void *p, xram_p x, int len)
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{
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for (len >>= 2; len > 0; len--, x += sizeof(u32)) {
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u32 val, *p32 = p;
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val = ((sbus_readw(x + 0x00UL) << 16) |
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(sbus_readw(x + 0x02UL)));
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*p32++ = val;
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p = p32;
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}
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}
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static inline void xram_copy_to(xram_p x, void *p, int len)
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{
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for (len >>= 2; len > 0; len--, x += sizeof(u32)) {
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u32 tmp, *p32 = p;
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tmp = *p32++;
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p = p32;
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sbus_writew(tmp >> 16, x + 0x00UL);
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sbus_writew(tmp, x + 0x02UL);
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}
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}
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static inline void xram_bzero(xram_p x, int len)
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{
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for (len >>= 1; len > 0; len--, x += sizeof(u16))
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sbus_writew(0, x);
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}
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/* Circular Queue */
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#define SOC_CQ_REQ_OFFSET (0x100 * sizeof(u16))
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#define SOC_CQ_RSP_OFFSET (0x110 * sizeof(u16))
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typedef struct {
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u32 address;
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u8 in;
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u8 out;
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u8 last;
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u8 seqno;
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} soc_hw_cq;
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#define SOC_PORT_A 0x0000 /* From/To Port A */
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#define SOC_PORT_B 0x0001 /* From/To Port A */
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#define SOC_FC_HDR 0x0002 /* Contains FC Header */
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#define SOC_NORSP 0x0004 /* Don't generate response nor interrupt */
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#define SOC_NOINT 0x0008 /* Generate response but not interrupt */
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#define SOC_XFERRDY 0x0010 /* Generate XFERRDY */
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#define SOC_IGNOREPARAM 0x0020 /* Ignore PARAM field in the FC header */
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#define SOC_COMPLETE 0x0040 /* Command completed */
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#define SOC_UNSOLICITED 0x0080 /* For request this is the packet to establish unsolicited pools, */
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/* for rsp this is unsolicited packet */
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#define SOC_STATUS 0x0100 /* State change (on/off line) */
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typedef struct {
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u32 token;
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u16 flags;
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u8 class;
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u8 segcnt;
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u32 bytecnt;
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} soc_hdr;
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typedef struct {
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u32 base;
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u32 count;
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} soc_data;
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#define SOC_CQTYPE_OUTBOUND 0x01
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#define SOC_CQTYPE_INBOUND 0x02
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#define SOC_CQTYPE_SIMPLE 0x03
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#define SOC_CQTYPE_IO_WRITE 0x04
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#define SOC_CQTYPE_IO_READ 0x05
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#define SOC_CQTYPE_UNSOLICITED 0x06
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#define SOC_CQTYPE_DIAG 0x07
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#define SOC_CQTYPE_OFFLINE 0x08
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#define SOC_CQTYPE_RESPONSE 0x10
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#define SOC_CQTYPE_INLINE 0x20
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#define SOC_CQFLAGS_CONT 0x01
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#define SOC_CQFLAGS_FULL 0x02
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#define SOC_CQFLAGS_BADHDR 0x04
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#define SOC_CQFLAGS_BADPKT 0x08
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typedef struct {
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soc_hdr shdr;
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soc_data data[3];
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fc_hdr fchdr;
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u8 count;
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u8 type;
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u8 flags;
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u8 seqno;
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} soc_req;
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#define SOC_OK 0
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#define SOC_P_RJT 2
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#define SOC_F_RJT 3
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#define SOC_P_BSY 4
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#define SOC_F_BSY 5
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#define SOC_ONLINE 0x10
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#define SOC_OFFLINE 0x11
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#define SOC_TIMEOUT 0x12
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#define SOC_OVERRUN 0x13
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#define SOC_UNKOWN_CQ_TYPE 0x20
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#define SOC_BAD_SEG_CNT 0x21
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#define SOC_MAX_XCHG_EXCEEDED 0x22
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#define SOC_BAD_XID 0x23
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#define SOC_XCHG_BUSY 0x24
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#define SOC_BAD_POOL_ID 0x25
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#define SOC_INSUFFICIENT_CQES 0x26
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#define SOC_ALLOC_FAIL 0x27
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#define SOC_BAD_SID 0x28
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#define SOC_NO_SEG_INIT 0x29
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typedef struct {
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soc_hdr shdr;
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u32 status;
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soc_data data;
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u8 xxx1[12];
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fc_hdr fchdr;
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u8 count;
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u8 type;
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u8 flags;
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u8 seqno;
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} soc_rsp;
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/* }}} */
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/* Now our software structures and constants we use to drive the beast {{{ */
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#define SOC_CQ_REQ0_SIZE 4
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#define SOC_CQ_REQ1_SIZE 64
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#define SOC_CQ_RSP0_SIZE 8
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#define SOC_CQ_RSP1_SIZE 4
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#define SOC_SOLICITED_RSP_Q 0
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#define SOC_UNSOLICITED_RSP_Q 1
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struct soc;
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typedef struct {
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/* This must come first */
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fc_channel fc;
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struct soc *s;
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u16 flags;
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u16 mask;
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} soc_port;
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typedef struct {
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soc_hw_cq __iomem *hw_cq; /* Related XRAM cq */
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soc_req __iomem *pool;
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u8 in;
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u8 out;
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u8 last;
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u8 seqno;
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} soc_cq_rsp;
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typedef struct {
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soc_hw_cq __iomem *hw_cq; /* Related XRAM cq */
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soc_req *pool;
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u8 in;
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u8 out;
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u8 last;
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u8 seqno;
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} soc_cq_req;
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struct soc {
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spinlock_t lock;
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soc_port port[2]; /* Every SOC has one or two FC ports */
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soc_cq_req req[2]; /* Request CQs */
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soc_cq_rsp rsp[2]; /* Response CQs */
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int soc_no;
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void __iomem *regs;
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xram_p xram;
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fc_wwn wwn;
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u32 imask; /* Our copy of regs->imask */
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u32 cfg; /* Our copy of regs->cfg */
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char serv_params[80];
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struct soc *next;
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int curr_port; /* Which port will have priority to fcp_queue_empty */
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soc_req *req_cpu;
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u32 req_dvma;
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};
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/* }}} */
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#endif /* !(__SOC_H) */
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