159 lines
4.3 KiB
C
159 lines
4.3 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright(c) 2020 Intel Corporation. All rights reserved.
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//
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// Author: Fred Oh <fred.oh@linux.intel.com>
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//
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/*
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* Hardware interface for audio DSP on IceLake.
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*/
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#include <linux/kernel.h>
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#include <linux/kconfig.h>
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#include <linux/export.h>
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#include <linux/bits.h>
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#include "../ops.h"
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#include "hda.h"
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#include "hda-ipc.h"
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#include "../sof-audio.h"
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#define ICL_DSP_HPRO_CORE_ID 3
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static const struct snd_sof_debugfs_map icl_dsp_debugfs[] = {
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{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
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{"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
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};
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static int icl_dsp_core_stall(struct snd_sof_dev *sdev, unsigned int core_mask)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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const struct sof_intel_dsp_desc *chip = hda->desc;
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/* make sure core_mask in host managed cores */
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core_mask &= chip->host_managed_cores_mask;
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if (!core_mask) {
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dev_err(sdev->dev, "error: core_mask is not in host managed cores\n");
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return -EINVAL;
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}
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/* stall core */
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snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
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HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
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return 0;
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}
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/*
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* post fw run operation for ICL.
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* Core 3 will be powered up and in stall when HPRO is enabled
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*/
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static int icl_dsp_post_fw_run(struct snd_sof_dev *sdev)
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{
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struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
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int ret;
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if (sdev->first_boot) {
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struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
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ret = hda_sdw_startup(sdev);
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if (ret < 0) {
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dev_err(sdev->dev, "error: could not startup SoundWire links\n");
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return ret;
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}
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/* Check if IMR boot is usable */
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if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
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sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT)
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hdev->imrboot_supported = true;
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}
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hda_sdw_int_enable(sdev, true);
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/*
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* The recommended HW programming sequence for ICL is to
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* power up core 3 and keep it in stall if HPRO is enabled.
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*/
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if (!hda->clk_config_lpro) {
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ret = hda_dsp_enable_core(sdev, BIT(ICL_DSP_HPRO_CORE_ID));
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if (ret < 0) {
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dev_err(sdev->dev, "error: dsp core power up failed on core %d\n",
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ICL_DSP_HPRO_CORE_ID);
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return ret;
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}
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sdev->enabled_cores_mask |= BIT(ICL_DSP_HPRO_CORE_ID);
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sdev->dsp_core_ref_count[ICL_DSP_HPRO_CORE_ID]++;
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snd_sof_dsp_stall(sdev, BIT(ICL_DSP_HPRO_CORE_ID));
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}
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/* re-enable clock gating and power gating */
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return hda_dsp_ctrl_clock_power_gating(sdev, true);
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}
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/* Icelake ops */
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struct snd_sof_dsp_ops sof_icl_ops;
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EXPORT_SYMBOL_NS(sof_icl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
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int sof_icl_ops_init(struct snd_sof_dev *sdev)
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{
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/* common defaults */
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memcpy(&sof_icl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
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/* probe/remove/shutdown */
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sof_icl_ops.shutdown = hda_dsp_shutdown;
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/* doorbell */
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sof_icl_ops.irq_thread = cnl_ipc_irq_thread;
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/* ipc */
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sof_icl_ops.send_msg = cnl_ipc_send_msg;
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/* debug */
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sof_icl_ops.debug_map = icl_dsp_debugfs;
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sof_icl_ops.debug_map_count = ARRAY_SIZE(icl_dsp_debugfs);
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sof_icl_ops.ipc_dump = cnl_ipc_dump;
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/* pre/post fw run */
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sof_icl_ops.post_fw_run = icl_dsp_post_fw_run;
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/* firmware run */
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sof_icl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
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sof_icl_ops.stall = icl_dsp_core_stall;
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/* dsp core get/put */
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sof_icl_ops.core_get = hda_dsp_core_get;
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/* set DAI driver ops */
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hda_set_dai_drv_ops(sdev, &sof_icl_ops);
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return 0;
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};
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EXPORT_SYMBOL_NS(sof_icl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
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const struct sof_intel_dsp_desc icl_chip_info = {
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/* Icelake */
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.cores_num = 4,
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.init_core_mask = 1,
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.host_managed_cores_mask = GENMASK(3, 0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
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.ipc_ctl = CNL_DSP_REG_HIPCCTL,
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.rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
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.rom_init_timeout = 300,
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.ssp_count = ICL_SSP_COUNT,
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.ssp_base_offset = CNL_SSP_BASE_OFFSET,
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.sdw_shim_base = SDW_SHIM_BASE,
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.sdw_alh_base = SDW_ALH_BASE,
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.check_sdw_irq = hda_common_check_sdw_irq,
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.check_ipc_irq = hda_dsp_check_ipc_irq,
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.cl_init = cl_dsp_init,
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.hw_ip_version = SOF_INTEL_CAVS_2_0,
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};
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EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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