293 lines
8.1 KiB
C
293 lines
8.1 KiB
C
/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef ATH_H
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#define ATH_H
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#include <linux/skbuff.h>
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#include <linux/if_ether.h>
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#include <linux/spinlock.h>
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#include <net/mac80211.h>
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/*
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* The key cache is used for h/w cipher state and also for
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* tracking station state such as the current tx antenna.
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* We also setup a mapping table between key cache slot indices
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* and station state to short-circuit node lookups on rx.
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* Different parts have different size key caches. We handle
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* up to ATH_KEYMAX entries (could dynamically allocate state).
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*/
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#define ATH_KEYMAX 128 /* max key cache size we handle */
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static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
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struct ath_ani {
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bool caldone;
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unsigned int longcal_timer;
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unsigned int shortcal_timer;
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unsigned int resetcal_timer;
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unsigned int checkani_timer;
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struct timer_list timer;
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};
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struct ath_cycle_counters {
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u32 cycles;
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u32 rx_busy;
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u32 rx_frame;
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u32 tx_frame;
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};
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enum ath_device_state {
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ATH_HW_UNAVAILABLE,
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ATH_HW_INITIALIZED,
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};
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enum ath_bus_type {
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ATH_PCI,
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ATH_AHB,
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ATH_USB,
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};
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struct reg_dmn_pair_mapping {
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u16 regDmnEnum;
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u16 reg_5ghz_ctl;
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u16 reg_2ghz_ctl;
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};
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struct ath_regulatory {
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char alpha2[2];
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u16 country_code;
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u16 max_power_level;
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u16 current_rd;
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int16_t power_limit;
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struct reg_dmn_pair_mapping *regpair;
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};
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enum ath_crypt_caps {
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ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
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ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
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};
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struct ath_keyval {
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u8 kv_type;
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u8 kv_pad;
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u16 kv_len;
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u8 kv_val[16]; /* TK */
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u8 kv_mic[8]; /* Michael MIC key */
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u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
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* supports both MIC keys in the same key cache entry;
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* in that case, kv_mic is the RX key) */
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};
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enum ath_cipher {
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ATH_CIPHER_WEP = 0,
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ATH_CIPHER_AES_OCB = 1,
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ATH_CIPHER_AES_CCM = 2,
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ATH_CIPHER_CKIP = 3,
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ATH_CIPHER_TKIP = 4,
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ATH_CIPHER_CLR = 5,
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ATH_CIPHER_MIC = 127
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};
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/**
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* struct ath_ops - Register read/write operations
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*
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* @read: Register read
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* @multi_read: Multiple register read
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* @write: Register write
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* @enable_write_buffer: Enable multiple register writes
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* @write_flush: flush buffered register writes and disable buffering
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*/
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struct ath_ops {
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unsigned int (*read)(void *, u32 reg_offset);
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void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
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void (*write)(void *, u32 val, u32 reg_offset);
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void (*enable_write_buffer)(void *);
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void (*write_flush) (void *);
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u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
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};
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struct ath_common;
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struct ath_bus_ops;
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struct ath_common {
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void *ah;
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void *priv;
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struct ieee80211_hw *hw;
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int debug_mask;
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enum ath_device_state state;
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struct ath_ani ani;
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u16 cachelsz;
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u16 curaid;
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u8 macaddr[ETH_ALEN];
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u8 curbssid[ETH_ALEN];
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u8 bssidmask[ETH_ALEN];
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u32 rx_bufsize;
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u32 keymax;
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DECLARE_BITMAP(keymap, ATH_KEYMAX);
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DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
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DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
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enum ath_crypt_caps crypt_caps;
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unsigned int clockrate;
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spinlock_t cc_lock;
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struct ath_cycle_counters cc_ani;
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struct ath_cycle_counters cc_survey;
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struct ath_regulatory regulatory;
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struct ath_regulatory reg_world_copy;
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const struct ath_ops *ops;
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const struct ath_bus_ops *bus_ops;
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bool btcoex_enabled;
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bool disable_ani;
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bool bt_ant_diversity;
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};
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struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
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u32 len,
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gfp_t gfp_mask);
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void ath_hw_setbssidmask(struct ath_common *common);
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void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
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int ath_key_config(struct ath_common *common,
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struct ieee80211_vif *vif,
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struct ieee80211_sta *sta,
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struct ieee80211_key_conf *key);
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bool ath_hw_keyreset(struct ath_common *common, u16 entry);
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void ath_hw_cycle_counters_update(struct ath_common *common);
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int32_t ath_hw_get_listen_time(struct ath_common *common);
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__printf(3, 4)
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void ath_printk(const char *level, const struct ath_common *common,
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const char *fmt, ...);
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#define ath_emerg(common, fmt, ...) \
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ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
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#define ath_alert(common, fmt, ...) \
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ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
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#define ath_crit(common, fmt, ...) \
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ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
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#define ath_err(common, fmt, ...) \
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ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
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#define ath_warn(common, fmt, ...) \
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ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
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#define ath_notice(common, fmt, ...) \
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ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
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#define ath_info(common, fmt, ...) \
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ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
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/**
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* enum ath_debug_level - atheros wireless debug level
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*
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* @ATH_DBG_RESET: reset processing
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* @ATH_DBG_QUEUE: hardware queue management
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* @ATH_DBG_EEPROM: eeprom processing
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* @ATH_DBG_CALIBRATE: periodic calibration
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* @ATH_DBG_INTERRUPT: interrupt processing
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* @ATH_DBG_REGULATORY: regulatory processing
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* @ATH_DBG_ANI: adaptive noise immunitive processing
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* @ATH_DBG_XMIT: basic xmit operation
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* @ATH_DBG_BEACON: beacon handling
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* @ATH_DBG_CONFIG: configuration of the hardware
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* @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
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* @ATH_DBG_PS: power save processing
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* @ATH_DBG_HWTIMER: hardware timer handling
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* @ATH_DBG_BTCOEX: bluetooth coexistance
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* @ATH_DBG_BSTUCK: stuck beacons
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* @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
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* used exclusively for WLAN-BT coexistence starting from
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* AR9462.
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* @ATH_DBG_DFS: radar datection
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* @ATH_DBG_WOW: Wake on Wireless
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* @ATH_DBG_ANY: enable all debugging
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*
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* The debug level is used to control the amount and type of debugging output
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* we want to see. Each driver has its own method for enabling debugging and
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* modifying debug level states -- but this is typically done through a
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* module parameter 'debug' along with a respective 'debug' debugfs file
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* entry.
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*/
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enum ATH_DEBUG {
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ATH_DBG_RESET = 0x00000001,
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ATH_DBG_QUEUE = 0x00000002,
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ATH_DBG_EEPROM = 0x00000004,
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ATH_DBG_CALIBRATE = 0x00000008,
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ATH_DBG_INTERRUPT = 0x00000010,
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ATH_DBG_REGULATORY = 0x00000020,
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ATH_DBG_ANI = 0x00000040,
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ATH_DBG_XMIT = 0x00000080,
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ATH_DBG_BEACON = 0x00000100,
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ATH_DBG_CONFIG = 0x00000200,
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ATH_DBG_FATAL = 0x00000400,
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ATH_DBG_PS = 0x00000800,
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ATH_DBG_BTCOEX = 0x00001000,
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ATH_DBG_WMI = 0x00002000,
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ATH_DBG_BSTUCK = 0x00004000,
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ATH_DBG_MCI = 0x00008000,
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ATH_DBG_DFS = 0x00010000,
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ATH_DBG_WOW = 0x00020000,
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ATH_DBG_ANY = 0xffffffff
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};
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#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
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#ifdef CONFIG_ATH_DEBUG
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#define ath_dbg(common, dbg_mask, fmt, ...) \
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do { \
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if ((common)->debug_mask & ATH_DBG_##dbg_mask) \
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ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
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} while (0)
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#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
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#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
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#else
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static inline __attribute__ ((format (printf, 3, 4)))
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void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
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const char *fmt, ...)
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{
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}
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#define ath_dbg(common, dbg_mask, fmt, ...) \
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_ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
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#define ATH_DBG_WARN(foo, arg...) do {} while (0)
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#define ATH_DBG_WARN_ON_ONCE(foo) ({ \
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int __ret_warn_once = !!(foo); \
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unlikely(__ret_warn_once); \
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})
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#endif /* CONFIG_ATH_DEBUG */
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/** Returns string describing opmode, or NULL if unknown mode. */
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#ifdef CONFIG_ATH_DEBUG
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const char *ath_opmode_to_string(enum nl80211_iftype opmode);
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#else
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static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
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{
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return "UNKNOWN";
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}
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#endif
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#endif /* ATH_H */
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