417 lines
10 KiB
C
417 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ADC driver for the Ingenic JZ47xx SoCs
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* Copyright (c) 2019 Artur Rojek <contact@artur-rojek.eu>
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*
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* based on drivers/mfd/jz4740-adc.c
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*/
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#include <dt-bindings/iio/adc/ingenic,adc.h>
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#include <linux/clk.h>
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#include <linux/iio/iio.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#define JZ_ADC_REG_ENABLE 0x00
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#define JZ_ADC_REG_CFG 0x04
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#define JZ_ADC_REG_CTRL 0x08
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#define JZ_ADC_REG_STATUS 0x0c
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#define JZ_ADC_REG_ADTCH 0x18
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#define JZ_ADC_REG_ADBDAT 0x1c
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#define JZ_ADC_REG_ADSDAT 0x20
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#define JZ_ADC_REG_ADCLK 0x28
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#define JZ_ADC_REG_CFG_BAT_MD BIT(4)
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#define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
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#define JZ_ADC_REG_ADCLK_CLKDIV10US_LSB 16
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#define JZ_ADC_AUX_VREF 3300
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#define JZ_ADC_AUX_VREF_BITS 12
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#define JZ_ADC_BATTERY_LOW_VREF 2500
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#define JZ_ADC_BATTERY_LOW_VREF_BITS 12
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#define JZ4725B_ADC_BATTERY_HIGH_VREF 7500
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#define JZ4725B_ADC_BATTERY_HIGH_VREF_BITS 10
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#define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986)
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#define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12
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struct ingenic_adc;
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struct ingenic_adc_soc_data {
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unsigned int battery_high_vref;
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unsigned int battery_high_vref_bits;
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const int *battery_raw_avail;
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size_t battery_raw_avail_size;
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const int *battery_scale_avail;
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size_t battery_scale_avail_size;
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int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc);
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};
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struct ingenic_adc {
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void __iomem *base;
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struct clk *clk;
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struct mutex lock;
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const struct ingenic_adc_soc_data *soc_data;
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bool low_vref_mode;
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};
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static void ingenic_adc_set_config(struct ingenic_adc *adc,
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uint32_t mask,
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uint32_t val)
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{
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uint32_t cfg;
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clk_enable(adc->clk);
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mutex_lock(&adc->lock);
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cfg = readl(adc->base + JZ_ADC_REG_CFG) & ~mask;
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cfg |= val;
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writel(cfg, adc->base + JZ_ADC_REG_CFG);
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mutex_unlock(&adc->lock);
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clk_disable(adc->clk);
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}
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static void ingenic_adc_enable(struct ingenic_adc *adc,
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int engine,
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bool enabled)
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{
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u8 val;
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mutex_lock(&adc->lock);
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val = readb(adc->base + JZ_ADC_REG_ENABLE);
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if (enabled)
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val |= BIT(engine);
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else
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val &= ~BIT(engine);
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writeb(val, adc->base + JZ_ADC_REG_ENABLE);
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mutex_unlock(&adc->lock);
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}
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static int ingenic_adc_capture(struct ingenic_adc *adc,
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int engine)
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{
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u8 val;
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int ret;
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ingenic_adc_enable(adc, engine, true);
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ret = readb_poll_timeout(adc->base + JZ_ADC_REG_ENABLE, val,
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!(val & BIT(engine)), 250, 1000);
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if (ret)
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ingenic_adc_enable(adc, engine, false);
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return ret;
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}
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static int ingenic_adc_write_raw(struct iio_dev *iio_dev,
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struct iio_chan_spec const *chan,
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int val,
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int val2,
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long m)
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{
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struct ingenic_adc *adc = iio_priv(iio_dev);
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switch (m) {
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case IIO_CHAN_INFO_SCALE:
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switch (chan->channel) {
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case INGENIC_ADC_BATTERY:
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if (val > JZ_ADC_BATTERY_LOW_VREF) {
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ingenic_adc_set_config(adc,
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JZ_ADC_REG_CFG_BAT_MD,
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0);
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adc->low_vref_mode = false;
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} else {
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ingenic_adc_set_config(adc,
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JZ_ADC_REG_CFG_BAT_MD,
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JZ_ADC_REG_CFG_BAT_MD);
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adc->low_vref_mode = true;
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}
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return 0;
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default:
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return -EINVAL;
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}
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default:
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return -EINVAL;
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}
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}
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static const int jz4725b_adc_battery_raw_avail[] = {
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0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
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};
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static const int jz4725b_adc_battery_scale_avail[] = {
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JZ4725B_ADC_BATTERY_HIGH_VREF, JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
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JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
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};
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static const int jz4740_adc_battery_raw_avail[] = {
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0, 1, (1 << JZ_ADC_BATTERY_LOW_VREF_BITS) - 1,
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};
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static const int jz4740_adc_battery_scale_avail[] = {
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JZ4740_ADC_BATTERY_HIGH_VREF, JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
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JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS,
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};
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static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc)
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{
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struct clk *parent_clk;
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unsigned long parent_rate, rate;
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unsigned int div_main, div_10us;
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parent_clk = clk_get_parent(adc->clk);
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if (!parent_clk) {
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dev_err(dev, "ADC clock has no parent\n");
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return -ENODEV;
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}
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parent_rate = clk_get_rate(parent_clk);
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/*
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* The JZ4725B ADC works at 500 kHz to 8 MHz.
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* We pick the highest rate possible.
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* In practice we typically get 6 MHz, half of the 12 MHz EXT clock.
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*/
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div_main = DIV_ROUND_UP(parent_rate, 8000000);
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div_main = clamp(div_main, 1u, 64u);
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rate = parent_rate / div_main;
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if (rate < 500000 || rate > 8000000) {
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dev_err(dev, "No valid divider for ADC main clock\n");
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return -EINVAL;
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}
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/* We also need a divider that produces a 10us clock. */
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div_10us = DIV_ROUND_UP(rate, 100000);
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writel(((div_10us - 1) << JZ_ADC_REG_ADCLK_CLKDIV10US_LSB) |
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(div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB,
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adc->base + JZ_ADC_REG_ADCLK);
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return 0;
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}
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static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = {
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.battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF,
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.battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS,
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.battery_raw_avail = jz4725b_adc_battery_raw_avail,
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.battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail),
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.battery_scale_avail = jz4725b_adc_battery_scale_avail,
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.battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail),
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.init_clk_div = jz4725b_adc_init_clk_div,
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};
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static const struct ingenic_adc_soc_data jz4740_adc_soc_data = {
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.battery_high_vref = JZ4740_ADC_BATTERY_HIGH_VREF,
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.battery_high_vref_bits = JZ4740_ADC_BATTERY_HIGH_VREF_BITS,
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.battery_raw_avail = jz4740_adc_battery_raw_avail,
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.battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail),
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.battery_scale_avail = jz4740_adc_battery_scale_avail,
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.battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail),
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.init_clk_div = NULL, /* no ADCLK register on JZ4740 */
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};
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static int ingenic_adc_read_avail(struct iio_dev *iio_dev,
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struct iio_chan_spec const *chan,
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const int **vals,
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int *type,
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int *length,
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long m)
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{
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struct ingenic_adc *adc = iio_priv(iio_dev);
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switch (m) {
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case IIO_CHAN_INFO_RAW:
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*type = IIO_VAL_INT;
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*length = adc->soc_data->battery_raw_avail_size;
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*vals = adc->soc_data->battery_raw_avail;
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return IIO_AVAIL_RANGE;
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case IIO_CHAN_INFO_SCALE:
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*type = IIO_VAL_FRACTIONAL_LOG2;
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*length = adc->soc_data->battery_scale_avail_size;
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*vals = adc->soc_data->battery_scale_avail;
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return IIO_AVAIL_LIST;
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default:
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return -EINVAL;
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};
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}
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static int ingenic_adc_read_raw(struct iio_dev *iio_dev,
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struct iio_chan_spec const *chan,
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int *val,
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int *val2,
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long m)
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{
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struct ingenic_adc *adc = iio_priv(iio_dev);
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int ret;
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switch (m) {
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case IIO_CHAN_INFO_RAW:
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clk_enable(adc->clk);
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ret = ingenic_adc_capture(adc, chan->channel);
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if (ret) {
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clk_disable(adc->clk);
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return ret;
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}
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switch (chan->channel) {
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case INGENIC_ADC_AUX:
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*val = readw(adc->base + JZ_ADC_REG_ADSDAT);
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break;
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case INGENIC_ADC_BATTERY:
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*val = readw(adc->base + JZ_ADC_REG_ADBDAT);
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break;
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}
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clk_disable(adc->clk);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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switch (chan->channel) {
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case INGENIC_ADC_AUX:
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*val = JZ_ADC_AUX_VREF;
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*val2 = JZ_ADC_AUX_VREF_BITS;
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break;
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case INGENIC_ADC_BATTERY:
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if (adc->low_vref_mode) {
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*val = JZ_ADC_BATTERY_LOW_VREF;
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*val2 = JZ_ADC_BATTERY_LOW_VREF_BITS;
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} else {
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*val = adc->soc_data->battery_high_vref;
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*val2 = adc->soc_data->battery_high_vref_bits;
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}
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break;
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}
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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}
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static void ingenic_adc_clk_cleanup(void *data)
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{
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clk_unprepare(data);
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}
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static const struct iio_info ingenic_adc_info = {
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.write_raw = ingenic_adc_write_raw,
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.read_raw = ingenic_adc_read_raw,
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.read_avail = ingenic_adc_read_avail,
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};
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static const struct iio_chan_spec ingenic_channels[] = {
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{
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.extend_name = "aux",
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.type = IIO_VOLTAGE,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE),
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.indexed = 1,
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.channel = INGENIC_ADC_AUX,
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},
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{
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.extend_name = "battery",
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.type = IIO_VOLTAGE,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE),
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.info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW) |
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BIT(IIO_CHAN_INFO_SCALE),
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.indexed = 1,
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.channel = INGENIC_ADC_BATTERY,
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},
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};
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static int ingenic_adc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct iio_dev *iio_dev;
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struct ingenic_adc *adc;
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struct resource *mem_base;
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const struct ingenic_adc_soc_data *soc_data;
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int ret;
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soc_data = device_get_match_data(dev);
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if (!soc_data)
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return -EINVAL;
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iio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
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if (!iio_dev)
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return -ENOMEM;
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adc = iio_priv(iio_dev);
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mutex_init(&adc->lock);
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adc->soc_data = soc_data;
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mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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adc->base = devm_ioremap_resource(dev, mem_base);
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if (IS_ERR(adc->base))
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return PTR_ERR(adc->base);
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adc->clk = devm_clk_get(dev, "adc");
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if (IS_ERR(adc->clk)) {
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dev_err(dev, "Unable to get clock\n");
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return PTR_ERR(adc->clk);
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}
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ret = clk_prepare_enable(adc->clk);
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if (ret) {
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dev_err(dev, "Failed to enable clock\n");
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return ret;
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}
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/* Set clock dividers. */
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if (soc_data->init_clk_div) {
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ret = soc_data->init_clk_div(dev, adc);
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if (ret) {
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clk_disable_unprepare(adc->clk);
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return ret;
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}
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}
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/* Put hardware in a known passive state. */
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writeb(0x00, adc->base + JZ_ADC_REG_ENABLE);
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writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
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clk_disable(adc->clk);
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ret = devm_add_action_or_reset(dev, ingenic_adc_clk_cleanup, adc->clk);
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if (ret) {
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dev_err(dev, "Unable to add action\n");
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return ret;
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}
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iio_dev->dev.parent = dev;
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iio_dev->name = "jz-adc";
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iio_dev->modes = INDIO_DIRECT_MODE;
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iio_dev->channels = ingenic_channels;
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iio_dev->num_channels = ARRAY_SIZE(ingenic_channels);
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iio_dev->info = &ingenic_adc_info;
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ret = devm_iio_device_register(dev, iio_dev);
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if (ret)
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dev_err(dev, "Unable to register IIO device\n");
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return ret;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id ingenic_adc_of_match[] = {
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{ .compatible = "ingenic,jz4725b-adc", .data = &jz4725b_adc_soc_data, },
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{ .compatible = "ingenic,jz4740-adc", .data = &jz4740_adc_soc_data, },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ingenic_adc_of_match);
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#endif
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static struct platform_driver ingenic_adc_driver = {
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.driver = {
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.name = "ingenic-adc",
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.of_match_table = of_match_ptr(ingenic_adc_of_match),
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},
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.probe = ingenic_adc_probe,
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};
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module_platform_driver(ingenic_adc_driver);
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MODULE_LICENSE("GPL v2");
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