585 lines
15 KiB
C
585 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* CPU PMU driver for the Apple M1 and derivatives
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*
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* Copyright (C) 2021 Google LLC
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*
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* Author: Marc Zyngier <maz@kernel.org>
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*
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* Most of the information used in this driver was provided by the
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* Asahi Linux project. The rest was experimentally discovered.
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*/
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#include <linux/of.h>
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#include <linux/perf/arm_pmu.h>
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#include <linux/platform_device.h>
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#include <asm/apple_m1_pmu.h>
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#include <asm/irq_regs.h>
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#include <asm/perf_event.h>
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#define M1_PMU_NR_COUNTERS 10
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#define M1_PMU_CFG_EVENT GENMASK(7, 0)
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#define ANY_BUT_0_1 GENMASK(9, 2)
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#define ONLY_2_TO_7 GENMASK(7, 2)
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#define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6))
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#define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7))
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/*
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* Description of the events we actually know about, as well as those with
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* a specific counter affinity. Yes, this is a grand total of two known
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* counters, and the rest is anybody's guess.
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*
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* Not all counters can count all events. Counters #0 and #1 are wired to
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* count cycles and instructions respectively, and some events have
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* bizarre mappings (every other counter, or even *one* counter). These
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* restrictions equally apply to both P and E cores.
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*
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* It is worth noting that the PMUs attached to P and E cores are likely
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* to be different because the underlying uarches are different. At the
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* moment, we don't really need to distinguish between the two because we
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* know next to nothing about the events themselves, and we already have
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* per cpu-type PMU abstractions.
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*
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* If we eventually find out that the events are different across
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* implementations, we'll have to introduce per cpu-type tables.
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*/
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enum m1_pmu_events {
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M1_PMU_PERFCTR_UNKNOWN_01 = 0x01,
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M1_PMU_PERFCTR_CPU_CYCLES = 0x02,
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M1_PMU_PERFCTR_INSTRUCTIONS = 0x8c,
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M1_PMU_PERFCTR_UNKNOWN_8d = 0x8d,
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M1_PMU_PERFCTR_UNKNOWN_8e = 0x8e,
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M1_PMU_PERFCTR_UNKNOWN_8f = 0x8f,
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M1_PMU_PERFCTR_UNKNOWN_90 = 0x90,
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M1_PMU_PERFCTR_UNKNOWN_93 = 0x93,
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M1_PMU_PERFCTR_UNKNOWN_94 = 0x94,
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M1_PMU_PERFCTR_UNKNOWN_95 = 0x95,
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M1_PMU_PERFCTR_UNKNOWN_96 = 0x96,
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M1_PMU_PERFCTR_UNKNOWN_97 = 0x97,
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M1_PMU_PERFCTR_UNKNOWN_98 = 0x98,
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M1_PMU_PERFCTR_UNKNOWN_99 = 0x99,
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M1_PMU_PERFCTR_UNKNOWN_9a = 0x9a,
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M1_PMU_PERFCTR_UNKNOWN_9b = 0x9b,
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M1_PMU_PERFCTR_UNKNOWN_9c = 0x9c,
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M1_PMU_PERFCTR_UNKNOWN_9f = 0x9f,
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M1_PMU_PERFCTR_UNKNOWN_bf = 0xbf,
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M1_PMU_PERFCTR_UNKNOWN_c0 = 0xc0,
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M1_PMU_PERFCTR_UNKNOWN_c1 = 0xc1,
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M1_PMU_PERFCTR_UNKNOWN_c4 = 0xc4,
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M1_PMU_PERFCTR_UNKNOWN_c5 = 0xc5,
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M1_PMU_PERFCTR_UNKNOWN_c6 = 0xc6,
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M1_PMU_PERFCTR_UNKNOWN_c8 = 0xc8,
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M1_PMU_PERFCTR_UNKNOWN_ca = 0xca,
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M1_PMU_PERFCTR_UNKNOWN_cb = 0xcb,
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M1_PMU_PERFCTR_UNKNOWN_f5 = 0xf5,
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M1_PMU_PERFCTR_UNKNOWN_f6 = 0xf6,
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M1_PMU_PERFCTR_UNKNOWN_f7 = 0xf7,
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M1_PMU_PERFCTR_UNKNOWN_f8 = 0xf8,
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M1_PMU_PERFCTR_UNKNOWN_fd = 0xfd,
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M1_PMU_PERFCTR_LAST = M1_PMU_CFG_EVENT,
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/*
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* From this point onwards, these are not actual HW events,
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* but attributes that get stored in hw->config_base.
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*/
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M1_PMU_CFG_COUNT_USER = BIT(8),
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M1_PMU_CFG_COUNT_KERNEL = BIT(9),
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};
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/*
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* Per-event affinity table. Most events can be installed on counter
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* 2-9, but there are a number of exceptions. Note that this table
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* has been created experimentally, and I wouldn't be surprised if more
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* counters had strange affinities.
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*/
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static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_LAST + 1] = {
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[0 ... M1_PMU_PERFCTR_LAST] = ANY_BUT_0_1,
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[M1_PMU_PERFCTR_UNKNOWN_01] = BIT(7),
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[M1_PMU_PERFCTR_CPU_CYCLES] = ANY_BUT_0_1 | BIT(0),
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[M1_PMU_PERFCTR_INSTRUCTIONS] = BIT(7) | BIT(1),
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[M1_PMU_PERFCTR_UNKNOWN_8d] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_8e] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_8f] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_90] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_93] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_94] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_95] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_96] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_97] = BIT(7),
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[M1_PMU_PERFCTR_UNKNOWN_98] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_99] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_9a] = BIT(7),
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[M1_PMU_PERFCTR_UNKNOWN_9b] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_9c] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_9f] = BIT(7),
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[M1_PMU_PERFCTR_UNKNOWN_bf] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_c0] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_c1] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_c4] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_c5] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_c6] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_c8] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_ca] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_cb] = ONLY_5_6_7,
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[M1_PMU_PERFCTR_UNKNOWN_f5] = ONLY_2_4_6,
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[M1_PMU_PERFCTR_UNKNOWN_f6] = ONLY_2_4_6,
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[M1_PMU_PERFCTR_UNKNOWN_f7] = ONLY_2_4_6,
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[M1_PMU_PERFCTR_UNKNOWN_f8] = ONLY_2_TO_7,
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[M1_PMU_PERFCTR_UNKNOWN_fd] = ONLY_2_4_6,
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};
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static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] = {
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PERF_MAP_ALL_UNSUPPORTED,
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[PERF_COUNT_HW_CPU_CYCLES] = M1_PMU_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = M1_PMU_PERFCTR_INSTRUCTIONS,
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/* No idea about the rest yet */
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};
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/* sysfs definitions */
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static ssize_t m1_pmu_events_sysfs_show(struct device *dev,
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struct device_attribute *attr,
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char *page)
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{
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struct perf_pmu_events_attr *pmu_attr;
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pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
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return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
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}
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#define M1_PMU_EVENT_ATTR(name, config) \
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PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config)
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static struct attribute *m1_pmu_event_attrs[] = {
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M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CPU_CYCLES),
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M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INSTRUCTIONS),
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NULL,
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};
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static const struct attribute_group m1_pmu_events_attr_group = {
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.name = "events",
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.attrs = m1_pmu_event_attrs,
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};
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PMU_FORMAT_ATTR(event, "config:0-7");
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static struct attribute *m1_pmu_format_attrs[] = {
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&format_attr_event.attr,
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NULL,
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};
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static const struct attribute_group m1_pmu_format_attr_group = {
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.name = "format",
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.attrs = m1_pmu_format_attrs,
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};
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/* Low level accessors. No synchronisation. */
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#define PMU_READ_COUNTER(_idx) \
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case _idx: return read_sysreg_s(SYS_IMP_APL_PMC## _idx ##_EL1)
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#define PMU_WRITE_COUNTER(_val, _idx) \
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case _idx: \
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write_sysreg_s(_val, SYS_IMP_APL_PMC## _idx ##_EL1); \
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return
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static u64 m1_pmu_read_hw_counter(unsigned int index)
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{
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switch (index) {
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PMU_READ_COUNTER(0);
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PMU_READ_COUNTER(1);
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PMU_READ_COUNTER(2);
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PMU_READ_COUNTER(3);
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PMU_READ_COUNTER(4);
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PMU_READ_COUNTER(5);
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PMU_READ_COUNTER(6);
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PMU_READ_COUNTER(7);
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PMU_READ_COUNTER(8);
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PMU_READ_COUNTER(9);
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}
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BUG();
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}
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static void m1_pmu_write_hw_counter(u64 val, unsigned int index)
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{
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switch (index) {
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PMU_WRITE_COUNTER(val, 0);
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PMU_WRITE_COUNTER(val, 1);
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PMU_WRITE_COUNTER(val, 2);
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PMU_WRITE_COUNTER(val, 3);
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PMU_WRITE_COUNTER(val, 4);
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PMU_WRITE_COUNTER(val, 5);
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PMU_WRITE_COUNTER(val, 6);
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PMU_WRITE_COUNTER(val, 7);
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PMU_WRITE_COUNTER(val, 8);
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PMU_WRITE_COUNTER(val, 9);
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}
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BUG();
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}
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#define get_bit_offset(index, mask) (__ffs(mask) + (index))
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static void __m1_pmu_enable_counter(unsigned int index, bool en)
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{
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u64 val, bit;
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switch (index) {
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case 0 ... 7:
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bit = BIT(get_bit_offset(index, PMCR0_CNT_ENABLE_0_7));
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break;
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case 8 ... 9:
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bit = BIT(get_bit_offset(index - 8, PMCR0_CNT_ENABLE_8_9));
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break;
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default:
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BUG();
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}
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val = read_sysreg_s(SYS_IMP_APL_PMCR0_EL1);
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if (en)
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val |= bit;
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else
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val &= ~bit;
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write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1);
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}
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static void m1_pmu_enable_counter(unsigned int index)
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{
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__m1_pmu_enable_counter(index, true);
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}
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static void m1_pmu_disable_counter(unsigned int index)
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{
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__m1_pmu_enable_counter(index, false);
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}
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static void __m1_pmu_enable_counter_interrupt(unsigned int index, bool en)
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{
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u64 val, bit;
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switch (index) {
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case 0 ... 7:
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bit = BIT(get_bit_offset(index, PMCR0_PMI_ENABLE_0_7));
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break;
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case 8 ... 9:
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bit = BIT(get_bit_offset(index - 8, PMCR0_PMI_ENABLE_8_9));
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break;
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default:
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BUG();
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}
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val = read_sysreg_s(SYS_IMP_APL_PMCR0_EL1);
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if (en)
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val |= bit;
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else
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val &= ~bit;
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write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1);
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}
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static void m1_pmu_enable_counter_interrupt(unsigned int index)
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{
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__m1_pmu_enable_counter_interrupt(index, true);
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}
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static void m1_pmu_disable_counter_interrupt(unsigned int index)
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{
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__m1_pmu_enable_counter_interrupt(index, false);
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}
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static void m1_pmu_configure_counter(unsigned int index, u8 event,
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bool user, bool kernel)
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{
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u64 val, user_bit, kernel_bit;
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int shift;
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switch (index) {
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case 0 ... 7:
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user_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7));
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kernel_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL1_0_7));
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break;
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case 8 ... 9:
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user_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL0_8_9));
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kernel_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL1_8_9));
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break;
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default:
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BUG();
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}
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val = read_sysreg_s(SYS_IMP_APL_PMCR1_EL1);
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if (user)
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val |= user_bit;
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else
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val &= ~user_bit;
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if (kernel)
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val |= kernel_bit;
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else
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val &= ~kernel_bit;
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write_sysreg_s(val, SYS_IMP_APL_PMCR1_EL1);
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/*
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* Counters 0 and 1 have fixed events. For anything else,
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* place the event at the expected location in the relevant
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* register (PMESR0 holds the event configuration for counters
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* 2-5, resp. PMESR1 for counters 6-9).
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*/
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switch (index) {
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case 0 ... 1:
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break;
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case 2 ... 5:
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shift = (index - 2) * 8;
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val = read_sysreg_s(SYS_IMP_APL_PMESR0_EL1);
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val &= ~((u64)0xff << shift);
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val |= (u64)event << shift;
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write_sysreg_s(val, SYS_IMP_APL_PMESR0_EL1);
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break;
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case 6 ... 9:
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shift = (index - 6) * 8;
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val = read_sysreg_s(SYS_IMP_APL_PMESR1_EL1);
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val &= ~((u64)0xff << shift);
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val |= (u64)event << shift;
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write_sysreg_s(val, SYS_IMP_APL_PMESR1_EL1);
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break;
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}
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}
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/* arm_pmu backend */
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static void m1_pmu_enable_event(struct perf_event *event)
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{
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bool user, kernel;
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u8 evt;
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evt = event->hw.config_base & M1_PMU_CFG_EVENT;
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user = event->hw.config_base & M1_PMU_CFG_COUNT_USER;
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kernel = event->hw.config_base & M1_PMU_CFG_COUNT_KERNEL;
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m1_pmu_disable_counter_interrupt(event->hw.idx);
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m1_pmu_disable_counter(event->hw.idx);
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isb();
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m1_pmu_configure_counter(event->hw.idx, evt, user, kernel);
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m1_pmu_enable_counter(event->hw.idx);
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m1_pmu_enable_counter_interrupt(event->hw.idx);
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isb();
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}
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static void m1_pmu_disable_event(struct perf_event *event)
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{
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m1_pmu_disable_counter_interrupt(event->hw.idx);
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m1_pmu_disable_counter(event->hw.idx);
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isb();
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}
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static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cpu_pmu)
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{
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struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
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struct pt_regs *regs;
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u64 overflow, state;
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int idx;
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overflow = read_sysreg_s(SYS_IMP_APL_PMSR_EL1);
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if (!overflow) {
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/* Spurious interrupt? */
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state = read_sysreg_s(SYS_IMP_APL_PMCR0_EL1);
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state &= ~PMCR0_IACT;
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write_sysreg_s(state, SYS_IMP_APL_PMCR0_EL1);
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isb();
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return IRQ_NONE;
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}
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cpu_pmu->stop(cpu_pmu);
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regs = get_irq_regs();
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for (idx = 0; idx < cpu_pmu->num_events; idx++) {
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struct perf_event *event = cpuc->events[idx];
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struct perf_sample_data data;
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if (!event)
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continue;
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armpmu_event_update(event);
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perf_sample_data_init(&data, 0, event->hw.last_period);
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if (!armpmu_event_set_period(event))
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continue;
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if (perf_event_overflow(event, &data, regs))
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m1_pmu_disable_event(event);
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}
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cpu_pmu->start(cpu_pmu);
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return IRQ_HANDLED;
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}
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static u64 m1_pmu_read_counter(struct perf_event *event)
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{
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return m1_pmu_read_hw_counter(event->hw.idx);
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}
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static void m1_pmu_write_counter(struct perf_event *event, u64 value)
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{
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m1_pmu_write_hw_counter(value, event->hw.idx);
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isb();
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}
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static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc,
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struct perf_event *event)
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{
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unsigned long evtype = event->hw.config_base & M1_PMU_CFG_EVENT;
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unsigned long affinity = m1_pmu_event_affinity[evtype];
|
|
int idx;
|
|
|
|
/*
|
|
* Place the event on the first free counter that can count
|
|
* this event.
|
|
*
|
|
* We could do a better job if we had a view of all the events
|
|
* counting on the PMU at any given time, and by placing the
|
|
* most constraining events first.
|
|
*/
|
|
for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) {
|
|
if (!test_and_set_bit(idx, cpuc->used_mask))
|
|
return idx;
|
|
}
|
|
|
|
return -EAGAIN;
|
|
}
|
|
|
|
static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc,
|
|
struct perf_event *event)
|
|
{
|
|
clear_bit(event->hw.idx, cpuc->used_mask);
|
|
}
|
|
|
|
static void __m1_pmu_set_mode(u8 mode)
|
|
{
|
|
u64 val;
|
|
|
|
val = read_sysreg_s(SYS_IMP_APL_PMCR0_EL1);
|
|
val &= ~(PMCR0_IMODE | PMCR0_IACT);
|
|
val |= FIELD_PREP(PMCR0_IMODE, mode);
|
|
write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1);
|
|
isb();
|
|
}
|
|
|
|
static void m1_pmu_start(struct arm_pmu *cpu_pmu)
|
|
{
|
|
__m1_pmu_set_mode(PMCR0_IMODE_FIQ);
|
|
}
|
|
|
|
static void m1_pmu_stop(struct arm_pmu *cpu_pmu)
|
|
{
|
|
__m1_pmu_set_mode(PMCR0_IMODE_OFF);
|
|
}
|
|
|
|
static int m1_pmu_map_event(struct perf_event *event)
|
|
{
|
|
/*
|
|
* Although the counters are 48bit wide, bit 47 is what
|
|
* triggers the overflow interrupt. Advertise the counters
|
|
* being 47bit wide to mimick the behaviour of the ARM PMU.
|
|
*/
|
|
event->hw.flags |= ARMPMU_EVT_47BIT;
|
|
return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT);
|
|
}
|
|
|
|
static void m1_pmu_reset(void *info)
|
|
{
|
|
int i;
|
|
|
|
__m1_pmu_set_mode(PMCR0_IMODE_OFF);
|
|
|
|
for (i = 0; i < M1_PMU_NR_COUNTERS; i++) {
|
|
m1_pmu_disable_counter(i);
|
|
m1_pmu_disable_counter_interrupt(i);
|
|
m1_pmu_write_hw_counter(0, i);
|
|
}
|
|
|
|
isb();
|
|
}
|
|
|
|
static int m1_pmu_set_event_filter(struct hw_perf_event *event,
|
|
struct perf_event_attr *attr)
|
|
{
|
|
unsigned long config_base = 0;
|
|
|
|
if (!attr->exclude_guest)
|
|
return -EINVAL;
|
|
if (!attr->exclude_kernel)
|
|
config_base |= M1_PMU_CFG_COUNT_KERNEL;
|
|
if (!attr->exclude_user)
|
|
config_base |= M1_PMU_CFG_COUNT_USER;
|
|
|
|
event->config_base = config_base;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int m1_pmu_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
cpu_pmu->handle_irq = m1_pmu_handle_irq;
|
|
cpu_pmu->enable = m1_pmu_enable_event;
|
|
cpu_pmu->disable = m1_pmu_disable_event;
|
|
cpu_pmu->read_counter = m1_pmu_read_counter;
|
|
cpu_pmu->write_counter = m1_pmu_write_counter;
|
|
cpu_pmu->get_event_idx = m1_pmu_get_event_idx;
|
|
cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx;
|
|
cpu_pmu->start = m1_pmu_start;
|
|
cpu_pmu->stop = m1_pmu_stop;
|
|
cpu_pmu->map_event = m1_pmu_map_event;
|
|
cpu_pmu->reset = m1_pmu_reset;
|
|
cpu_pmu->set_event_filter = m1_pmu_set_event_filter;
|
|
|
|
cpu_pmu->num_events = M1_PMU_NR_COUNTERS;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;
|
|
cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &m1_pmu_format_attr_group;
|
|
return 0;
|
|
}
|
|
|
|
/* Device driver gunk */
|
|
static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
cpu_pmu->name = "apple_icestorm_pmu";
|
|
return m1_pmu_init(cpu_pmu);
|
|
}
|
|
|
|
static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu)
|
|
{
|
|
cpu_pmu->name = "apple_firestorm_pmu";
|
|
return m1_pmu_init(cpu_pmu);
|
|
}
|
|
|
|
static const struct of_device_id m1_pmu_of_device_ids[] = {
|
|
{ .compatible = "apple,icestorm-pmu", .data = m1_pmu_ice_init, },
|
|
{ .compatible = "apple,firestorm-pmu", .data = m1_pmu_fire_init, },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids);
|
|
|
|
static int m1_pmu_device_probe(struct platform_device *pdev)
|
|
{
|
|
return arm_pmu_device_probe(pdev, m1_pmu_of_device_ids, NULL);
|
|
}
|
|
|
|
static struct platform_driver m1_pmu_driver = {
|
|
.driver = {
|
|
.name = "apple-m1-cpu-pmu",
|
|
.of_match_table = m1_pmu_of_device_ids,
|
|
.suppress_bind_attrs = true,
|
|
},
|
|
.probe = m1_pmu_device_probe,
|
|
};
|
|
|
|
module_platform_driver(m1_pmu_driver);
|
|
MODULE_LICENSE("GPL v2");
|