751 lines
20 KiB
C
751 lines
20 KiB
C
/*
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* Copyright (C) 2015 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/**
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* DOC: VC4 CRTC module
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*
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* In VC4, the Pixel Valve is what most closely corresponds to the
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* DRM's concept of a CRTC. The PV generates video timings from the
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* output's clock plus its configuration. It pulls scaled pixels from
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* the HVS at that timing, and feeds it to the encoder.
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*
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* However, the DRM CRTC also collects the configuration of all the
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* DRM planes attached to it. As a result, this file also manages
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* setup of the VC4 HVS's display elements on the CRTC.
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*
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* The 2835 has 3 different pixel valves. pv0 in the audio power
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* domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
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* image domain can feed either HDMI or the SDTV controller. The
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* pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
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* SDTV, etc.) according to which output type is chosen in the mux.
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*
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* For power management, the pixel valve's registers are all clocked
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* by the AXI clock, while the timings and FIFOs make use of the
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* output-specific clock. Since the encoders also directly consume
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* the CPRMAN clocks, and know what timings they need, they are the
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* ones that set the clock.
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*/
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#include "drm_atomic.h"
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#include "drm_atomic_helper.h"
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#include "drm_crtc_helper.h"
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#include "linux/clk.h"
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#include "drm_fb_cma_helper.h"
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#include "linux/component.h"
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#include "linux/of_device.h"
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#include "vc4_drv.h"
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#include "vc4_regs.h"
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struct vc4_crtc {
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struct drm_crtc base;
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const struct vc4_crtc_data *data;
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void __iomem *regs;
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/* Which HVS channel we're using for our CRTC. */
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int channel;
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/* Pointer to the actual hardware display list memory for the
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* crtc.
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*/
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u32 __iomem *dlist;
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u32 dlist_size; /* in dwords */
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struct drm_pending_vblank_event *event;
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};
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static inline struct vc4_crtc *
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to_vc4_crtc(struct drm_crtc *crtc)
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{
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return (struct vc4_crtc *)crtc;
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}
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struct vc4_crtc_data {
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/* Which channel of the HVS this pixelvalve sources from. */
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int hvs_channel;
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enum vc4_encoder_type encoder0_type;
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enum vc4_encoder_type encoder1_type;
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};
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#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
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#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
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#define CRTC_REG(reg) { reg, #reg }
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static const struct {
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u32 reg;
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const char *name;
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} crtc_regs[] = {
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CRTC_REG(PV_CONTROL),
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CRTC_REG(PV_V_CONTROL),
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CRTC_REG(PV_VSYNCD),
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CRTC_REG(PV_HORZA),
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CRTC_REG(PV_HORZB),
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CRTC_REG(PV_VERTA),
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CRTC_REG(PV_VERTB),
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CRTC_REG(PV_VERTA_EVEN),
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CRTC_REG(PV_VERTB_EVEN),
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CRTC_REG(PV_INTEN),
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CRTC_REG(PV_INTSTAT),
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CRTC_REG(PV_STAT),
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CRTC_REG(PV_HACT_ACT),
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};
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static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
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DRM_INFO("0x%04x (%s): 0x%08x\n",
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crtc_regs[i].reg, crtc_regs[i].name,
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CRTC_READ(crtc_regs[i].reg));
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}
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}
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#ifdef CONFIG_DEBUG_FS
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int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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int crtc_index = (uintptr_t)node->info_ent->data;
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struct drm_crtc *crtc;
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struct vc4_crtc *vc4_crtc;
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int i;
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i = 0;
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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if (i == crtc_index)
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break;
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i++;
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}
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if (!crtc)
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return 0;
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vc4_crtc = to_vc4_crtc(crtc);
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for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
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seq_printf(m, "%s (0x%04x): 0x%08x\n",
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crtc_regs[i].name, crtc_regs[i].reg,
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CRTC_READ(crtc_regs[i].reg));
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}
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return 0;
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}
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#endif
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static void vc4_crtc_destroy(struct drm_crtc *crtc)
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{
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drm_crtc_cleanup(crtc);
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}
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static u32 vc4_get_fifo_full_level(u32 format)
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{
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static const u32 fifo_len_bytes = 64;
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static const u32 hvs_latency_pix = 6;
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switch (format) {
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case PV_CONTROL_FORMAT_DSIV_16:
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case PV_CONTROL_FORMAT_DSIC_16:
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return fifo_len_bytes - 2 * hvs_latency_pix;
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case PV_CONTROL_FORMAT_DSIV_18:
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return fifo_len_bytes - 14;
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case PV_CONTROL_FORMAT_24:
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case PV_CONTROL_FORMAT_DSIV_24:
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default:
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return fifo_len_bytes - 3 * hvs_latency_pix;
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}
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}
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/*
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* Returns the clock select bit for the connector attached to the
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* CRTC.
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*/
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static int vc4_get_clock_select(struct drm_crtc *crtc)
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{
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struct drm_connector *connector;
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drm_for_each_connector(connector, crtc->dev) {
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if (connector->state->crtc == crtc) {
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struct drm_encoder *encoder = connector->encoder;
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struct vc4_encoder *vc4_encoder =
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to_vc4_encoder(encoder);
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return vc4_encoder->clock_select;
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}
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}
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return -1;
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}
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static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct drm_crtc_state *state = crtc->state;
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struct drm_display_mode *mode = &state->adjusted_mode;
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bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
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u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
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u32 format = PV_CONTROL_FORMAT_24;
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bool debug_dump_regs = false;
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int clock_select = vc4_get_clock_select(crtc);
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
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vc4_crtc_dump_regs(vc4_crtc);
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}
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/* Reset the PV fifo. */
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CRTC_WRITE(PV_CONTROL, 0);
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CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
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CRTC_WRITE(PV_CONTROL, 0);
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CRTC_WRITE(PV_HORZA,
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VC4_SET_FIELD(mode->htotal - mode->hsync_end,
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PV_HORZA_HBP) |
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VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
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PV_HORZA_HSYNC));
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CRTC_WRITE(PV_HORZB,
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VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
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PV_HORZB_HFP) |
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VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
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if (interlace) {
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CRTC_WRITE(PV_VERTA_EVEN,
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
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PV_VERTA_VBP) |
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VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
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PV_VERTA_VSYNC));
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CRTC_WRITE(PV_VERTB_EVEN,
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VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
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PV_VERTB_VFP) |
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VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
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}
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CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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(interlace ? PV_VCONTROL_INTERLACE : 0));
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CRTC_WRITE(PV_CONTROL,
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VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
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VC4_SET_FIELD(vc4_get_fifo_full_level(format),
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PV_CONTROL_FIFO_LEVEL) |
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PV_CONTROL_CLR_AT_START |
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PV_CONTROL_TRIGGER_UNDERFLOW |
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PV_CONTROL_WAIT_HSTART |
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VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
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PV_CONTROL_FIFO_CLR |
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PV_CONTROL_EN);
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
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vc4_crtc_dump_regs(vc4_crtc);
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}
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}
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static void require_hvs_enabled(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
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SCALER_DISPCTRL_ENABLE);
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}
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static void vc4_crtc_disable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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u32 chan = vc4_crtc->channel;
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int ret;
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require_hvs_enabled(dev);
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CRTC_WRITE(PV_V_CONTROL,
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CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
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ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
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WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
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if (HVS_READ(SCALER_DISPCTRLX(chan)) &
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SCALER_DISPCTRLX_ENABLE) {
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HVS_WRITE(SCALER_DISPCTRLX(chan),
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SCALER_DISPCTRLX_RESET);
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/* While the docs say that reset is self-clearing, it
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* seems it doesn't actually.
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*/
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HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
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}
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/* Once we leave, the scaler should be disabled and its fifo empty. */
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WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
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WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
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SCALER_DISPSTATX_MODE) !=
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SCALER_DISPSTATX_MODE_DISABLED);
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WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
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(SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
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SCALER_DISPSTATX_EMPTY);
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}
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static void vc4_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct drm_crtc_state *state = crtc->state;
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struct drm_display_mode *mode = &state->adjusted_mode;
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require_hvs_enabled(dev);
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/* Turn on the scaler, which will wait for vstart to start
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* compositing.
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*/
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HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
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VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
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VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
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SCALER_DISPCTRLX_ENABLE);
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/* Turn on the pixel valve, which will emit the vstart signal. */
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CRTC_WRITE(PV_V_CONTROL,
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CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
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}
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static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct drm_plane *plane;
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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u32 dlist_count = 0;
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/* The pixelvalve can only feed one encoder (and encoders are
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* 1:1 with connectors.)
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*/
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if (hweight32(state->connector_mask) > 1)
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return -EINVAL;
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drm_atomic_crtc_state_for_each_plane(plane, state) {
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struct drm_plane_state *plane_state =
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state->state->plane_states[drm_plane_index(plane)];
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/* plane might not have changed, in which case take
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* current state:
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*/
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if (!plane_state)
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plane_state = plane->state;
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dlist_count += vc4_plane_dlist_size(plane_state);
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}
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dlist_count++; /* Account for SCALER_CTL0_END. */
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if (!vc4_crtc->dlist || dlist_count > vc4_crtc->dlist_size) {
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vc4_crtc->dlist = ((u32 __iomem *)vc4->hvs->dlist +
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HVS_BOOTLOADER_DLIST_END);
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vc4_crtc->dlist_size = ((SCALER_DLIST_SIZE >> 2) -
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HVS_BOOTLOADER_DLIST_END);
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if (dlist_count > vc4_crtc->dlist_size) {
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DRM_DEBUG_KMS("dlist too large for CRTC (%d > %d).\n",
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dlist_count, vc4_crtc->dlist_size);
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return -EINVAL;
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}
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}
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return 0;
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}
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static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct drm_plane *plane;
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bool debug_dump_regs = false;
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u32 __iomem *dlist_next = vc4_crtc->dlist;
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
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vc4_hvs_dump_state(dev);
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}
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/* Copy all the active planes' dlist contents to the hardware dlist.
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*
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* XXX: If the new display list was large enough that it
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* overlapped a currently-read display list, we need to do
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* something like disable scanout before putting in the new
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* list. For now, we're safe because we only have the two
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* planes.
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*/
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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dlist_next += vc4_plane_write_dlist(plane, dlist_next);
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}
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if (dlist_next == vc4_crtc->dlist) {
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/* If no planes were enabled, use the SCALER_CTL0_END
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* at the start of the display list memory (in the
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* bootloader section). We'll rewrite that
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* SCALER_CTL0_END, just in case, though.
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*/
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writel(SCALER_CTL0_END, vc4->hvs->dlist);
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HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 0);
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} else {
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writel(SCALER_CTL0_END, dlist_next);
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dlist_next++;
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HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
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(u32 __iomem *)vc4_crtc->dlist -
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(u32 __iomem *)vc4->hvs->dlist);
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/* Make the next display list start after ours. */
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vc4_crtc->dlist_size -= (dlist_next - vc4_crtc->dlist);
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vc4_crtc->dlist = dlist_next;
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}
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
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vc4_hvs_dump_state(dev);
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}
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if (crtc->state->event) {
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unsigned long flags;
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crtc->state->event->pipe = drm_crtc_index(crtc);
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WARN_ON(drm_crtc_vblank_get(crtc) != 0);
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spin_lock_irqsave(&dev->event_lock, flags);
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vc4_crtc->event = crtc->state->event;
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spin_unlock_irqrestore(&dev->event_lock, flags);
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crtc->state->event = NULL;
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}
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}
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int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
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CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
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return 0;
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}
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void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
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CRTC_WRITE(PV_INTEN, 0);
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}
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static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
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{
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struct drm_crtc *crtc = &vc4_crtc->base;
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struct drm_device *dev = crtc->dev;
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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if (vc4_crtc->event) {
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drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
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vc4_crtc->event = NULL;
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}
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
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{
|
|
struct vc4_crtc *vc4_crtc = data;
|
|
u32 stat = CRTC_READ(PV_INTSTAT);
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
if (stat & PV_INT_VFP_START) {
|
|
CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
|
|
drm_crtc_handle_vblank(&vc4_crtc->base);
|
|
vc4_crtc_handle_page_flip(vc4_crtc);
|
|
ret = IRQ_HANDLED;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
struct vc4_async_flip_state {
|
|
struct drm_crtc *crtc;
|
|
struct drm_framebuffer *fb;
|
|
struct drm_pending_vblank_event *event;
|
|
|
|
struct vc4_seqno_cb cb;
|
|
};
|
|
|
|
/* Called when the V3D execution for the BO being flipped to is done, so that
|
|
* we can actually update the plane's address to point to it.
|
|
*/
|
|
static void
|
|
vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
|
|
{
|
|
struct vc4_async_flip_state *flip_state =
|
|
container_of(cb, struct vc4_async_flip_state, cb);
|
|
struct drm_crtc *crtc = flip_state->crtc;
|
|
struct drm_device *dev = crtc->dev;
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
struct drm_plane *plane = crtc->primary;
|
|
|
|
vc4_plane_async_set_fb(plane, flip_state->fb);
|
|
if (flip_state->event) {
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
drm_crtc_send_vblank_event(crtc, flip_state->event);
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
}
|
|
|
|
drm_framebuffer_unreference(flip_state->fb);
|
|
kfree(flip_state);
|
|
|
|
up(&vc4->async_modeset);
|
|
}
|
|
|
|
/* Implements async (non-vblank-synced) page flips.
|
|
*
|
|
* The page flip ioctl needs to return immediately, so we grab the
|
|
* modeset semaphore on the pipe, and queue the address update for
|
|
* when V3D is done with the BO being flipped to.
|
|
*/
|
|
static int vc4_async_page_flip(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
struct drm_pending_vblank_event *event,
|
|
uint32_t flags)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
struct drm_plane *plane = crtc->primary;
|
|
int ret = 0;
|
|
struct vc4_async_flip_state *flip_state;
|
|
struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
|
|
struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
|
|
|
|
flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
|
|
if (!flip_state)
|
|
return -ENOMEM;
|
|
|
|
drm_framebuffer_reference(fb);
|
|
flip_state->fb = fb;
|
|
flip_state->crtc = crtc;
|
|
flip_state->event = event;
|
|
|
|
/* Make sure all other async modesetes have landed. */
|
|
ret = down_interruptible(&vc4->async_modeset);
|
|
if (ret) {
|
|
kfree(flip_state);
|
|
return ret;
|
|
}
|
|
|
|
/* Immediately update the plane's legacy fb pointer, so that later
|
|
* modeset prep sees the state that will be present when the semaphore
|
|
* is released.
|
|
*/
|
|
drm_atomic_set_fb_for_plane(plane->state, fb);
|
|
plane->fb = fb;
|
|
|
|
vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
|
|
vc4_async_page_flip_complete);
|
|
|
|
/* Driver takes ownership of state on successful async commit. */
|
|
return 0;
|
|
}
|
|
|
|
static int vc4_page_flip(struct drm_crtc *crtc,
|
|
struct drm_framebuffer *fb,
|
|
struct drm_pending_vblank_event *event,
|
|
uint32_t flags)
|
|
{
|
|
if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
|
|
return vc4_async_page_flip(crtc, fb, event, flags);
|
|
else
|
|
return drm_atomic_helper_page_flip(crtc, fb, event, flags);
|
|
}
|
|
|
|
static const struct drm_crtc_funcs vc4_crtc_funcs = {
|
|
.set_config = drm_atomic_helper_set_config,
|
|
.destroy = vc4_crtc_destroy,
|
|
.page_flip = vc4_page_flip,
|
|
.set_property = NULL,
|
|
.cursor_set = NULL, /* handled by drm_mode_cursor_universal */
|
|
.cursor_move = NULL, /* handled by drm_mode_cursor_universal */
|
|
.reset = drm_atomic_helper_crtc_reset,
|
|
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
|
|
};
|
|
|
|
static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
|
|
.mode_set_nofb = vc4_crtc_mode_set_nofb,
|
|
.disable = vc4_crtc_disable,
|
|
.enable = vc4_crtc_enable,
|
|
.atomic_check = vc4_crtc_atomic_check,
|
|
.atomic_flush = vc4_crtc_atomic_flush,
|
|
};
|
|
|
|
static const struct vc4_crtc_data pv0_data = {
|
|
.hvs_channel = 0,
|
|
.encoder0_type = VC4_ENCODER_TYPE_DSI0,
|
|
.encoder1_type = VC4_ENCODER_TYPE_DPI,
|
|
};
|
|
|
|
static const struct vc4_crtc_data pv1_data = {
|
|
.hvs_channel = 2,
|
|
.encoder0_type = VC4_ENCODER_TYPE_DSI1,
|
|
.encoder1_type = VC4_ENCODER_TYPE_SMI,
|
|
};
|
|
|
|
static const struct vc4_crtc_data pv2_data = {
|
|
.hvs_channel = 1,
|
|
.encoder0_type = VC4_ENCODER_TYPE_VEC,
|
|
.encoder1_type = VC4_ENCODER_TYPE_HDMI,
|
|
};
|
|
|
|
static const struct of_device_id vc4_crtc_dt_match[] = {
|
|
{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
|
|
{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
|
|
{ .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
|
|
{}
|
|
};
|
|
|
|
static void vc4_set_crtc_possible_masks(struct drm_device *drm,
|
|
struct drm_crtc *crtc)
|
|
{
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
|
struct drm_encoder *encoder;
|
|
|
|
drm_for_each_encoder(encoder, drm) {
|
|
struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
|
|
|
|
if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
|
|
vc4_encoder->clock_select = 0;
|
|
encoder->possible_crtcs |= drm_crtc_mask(crtc);
|
|
} else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
|
|
vc4_encoder->clock_select = 1;
|
|
encoder->possible_crtcs |= drm_crtc_mask(crtc);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct drm_device *drm = dev_get_drvdata(master);
|
|
struct vc4_dev *vc4 = to_vc4_dev(drm);
|
|
struct vc4_crtc *vc4_crtc;
|
|
struct drm_crtc *crtc;
|
|
struct drm_plane *primary_plane, *cursor_plane;
|
|
const struct of_device_id *match;
|
|
int ret;
|
|
|
|
vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
|
|
if (!vc4_crtc)
|
|
return -ENOMEM;
|
|
crtc = &vc4_crtc->base;
|
|
|
|
match = of_match_device(vc4_crtc_dt_match, dev);
|
|
if (!match)
|
|
return -ENODEV;
|
|
vc4_crtc->data = match->data;
|
|
|
|
vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
|
|
if (IS_ERR(vc4_crtc->regs))
|
|
return PTR_ERR(vc4_crtc->regs);
|
|
|
|
/* For now, we create just the primary and the legacy cursor
|
|
* planes. We should be able to stack more planes on easily,
|
|
* but to do that we would need to compute the bandwidth
|
|
* requirement of the plane configuration, and reject ones
|
|
* that will take too much.
|
|
*/
|
|
primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
|
|
if (IS_ERR(primary_plane)) {
|
|
dev_err(dev, "failed to construct primary plane\n");
|
|
ret = PTR_ERR(primary_plane);
|
|
goto err;
|
|
}
|
|
|
|
cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
|
|
if (IS_ERR(cursor_plane)) {
|
|
dev_err(dev, "failed to construct cursor plane\n");
|
|
ret = PTR_ERR(cursor_plane);
|
|
goto err_primary;
|
|
}
|
|
|
|
drm_crtc_init_with_planes(drm, crtc, primary_plane, cursor_plane,
|
|
&vc4_crtc_funcs, NULL);
|
|
drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
|
|
primary_plane->crtc = crtc;
|
|
cursor_plane->crtc = crtc;
|
|
vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
|
|
vc4_crtc->channel = vc4_crtc->data->hvs_channel;
|
|
|
|
CRTC_WRITE(PV_INTEN, 0);
|
|
CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
|
|
ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
|
|
vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
|
|
if (ret)
|
|
goto err_cursor;
|
|
|
|
vc4_set_crtc_possible_masks(drm, crtc);
|
|
|
|
platform_set_drvdata(pdev, vc4_crtc);
|
|
|
|
return 0;
|
|
|
|
err_cursor:
|
|
cursor_plane->funcs->destroy(cursor_plane);
|
|
err_primary:
|
|
primary_plane->funcs->destroy(primary_plane);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static void vc4_crtc_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
|
|
|
|
vc4_crtc_destroy(&vc4_crtc->base);
|
|
|
|
CRTC_WRITE(PV_INTEN, 0);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
}
|
|
|
|
static const struct component_ops vc4_crtc_ops = {
|
|
.bind = vc4_crtc_bind,
|
|
.unbind = vc4_crtc_unbind,
|
|
};
|
|
|
|
static int vc4_crtc_dev_probe(struct platform_device *pdev)
|
|
{
|
|
return component_add(&pdev->dev, &vc4_crtc_ops);
|
|
}
|
|
|
|
static int vc4_crtc_dev_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &vc4_crtc_ops);
|
|
return 0;
|
|
}
|
|
|
|
struct platform_driver vc4_crtc_driver = {
|
|
.probe = vc4_crtc_dev_probe,
|
|
.remove = vc4_crtc_dev_remove,
|
|
.driver = {
|
|
.name = "vc4_crtc",
|
|
.of_match_table = vc4_crtc_dt_match,
|
|
},
|
|
};
|