485 lines
13 KiB
C
485 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* DesignWare application register space functions for Keystone PCI controller
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*
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* Copyright (C) 2013-2014 Texas Instruments., Ltd.
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* http://www.ti.com
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*
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* Author: Murali Karicheri <m-karicheri2@ti.com>
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*/
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqreturn.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include "pcie-designware.h"
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#include "pci-keystone.h"
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/* Application register defines */
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#define LTSSM_EN_VAL 1
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#define LTSSM_STATE_MASK 0x1f
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#define LTSSM_STATE_L0 0x11
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#define DBI_CS2_EN_VAL 0x20
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#define OB_XLAT_EN_VAL 2
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/* Application registers */
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#define CMD_STATUS 0x004
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#define CFG_SETUP 0x008
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#define OB_SIZE 0x030
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#define CFG_PCIM_WIN_SZ_IDX 3
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#define CFG_PCIM_WIN_CNT 32
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#define SPACE0_REMOTE_CFG_OFFSET 0x1000
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#define OB_OFFSET_INDEX(n) (0x200 + (8 * n))
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#define OB_OFFSET_HI(n) (0x204 + (8 * n))
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/* IRQ register defines */
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#define IRQ_EOI 0x050
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#define IRQ_STATUS 0x184
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#define IRQ_ENABLE_SET 0x188
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#define IRQ_ENABLE_CLR 0x18c
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#define MSI_IRQ 0x054
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#define MSI0_IRQ_STATUS 0x104
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#define MSI0_IRQ_ENABLE_SET 0x108
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#define MSI0_IRQ_ENABLE_CLR 0x10c
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#define IRQ_STATUS 0x184
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#define MSI_IRQ_OFFSET 4
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/* Error IRQ bits */
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#define ERR_AER BIT(5) /* ECRC error */
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#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */
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#define ERR_CORR BIT(3) /* Correctable error */
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#define ERR_NONFATAL BIT(2) /* Non-fatal error */
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#define ERR_FATAL BIT(1) /* Fatal error */
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#define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */
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#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \
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ERR_NONFATAL | ERR_FATAL | ERR_SYS)
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#define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI)
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#define ERR_IRQ_STATUS_RAW 0x1c0
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#define ERR_IRQ_STATUS 0x1c4
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#define ERR_IRQ_ENABLE_SET 0x1c8
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#define ERR_IRQ_ENABLE_CLR 0x1cc
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/* Config space registers */
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#define DEBUG0 0x728
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#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
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static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
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u32 *bit_pos)
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{
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*reg_offset = offset % 8;
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*bit_pos = offset >> 3;
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}
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phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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return ks_pcie->app.start + MSI_IRQ;
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}
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static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
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{
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return readl(ks_pcie->va_app_base + offset);
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}
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static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val)
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{
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writel(val, ks_pcie->va_app_base + offset);
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}
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void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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struct device *dev = pci->dev;
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u32 pending, vector;
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int src, virq;
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pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
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/*
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* MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
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* shows 1, 9, 17, 25 and so forth
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*/
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for (src = 0; src < 4; src++) {
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if (BIT(src) & pending) {
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vector = offset + (src << 3);
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virq = irq_linear_revmap(pp->irq_domain, vector);
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dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
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src, vector, virq);
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generic_handle_irq(virq);
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}
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}
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}
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void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
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{
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u32 reg_offset, bit_pos;
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struct keystone_pcie *ks_pcie;
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struct dw_pcie *pci;
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pci = to_dw_pcie_from_pp(pp);
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ks_pcie = to_keystone_pcie(pci);
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update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
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ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
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BIT(bit_pos));
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ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
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}
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void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
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{
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u32 reg_offset, bit_pos;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
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ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
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BIT(bit_pos));
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}
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void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
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{
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u32 reg_offset, bit_pos;
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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update_reg_offset_bit_pos(irq, ®_offset, &bit_pos);
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ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
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BIT(bit_pos));
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}
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int ks_dw_pcie_msi_host_init(struct pcie_port *pp)
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{
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return dw_pcie_allocate_domains(pp);
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}
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void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
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{
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int i;
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for (i = 0; i < PCI_NUM_INTX; i++)
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ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
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}
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void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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struct device *dev = pci->dev;
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u32 pending;
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int virq;
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pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
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if (BIT(0) & pending) {
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virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
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dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
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generic_handle_irq(virq);
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}
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/* EOI the INTx interrupt */
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ks_dw_app_writel(ks_pcie, IRQ_EOI, offset);
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}
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void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
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{
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ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
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}
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irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
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{
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u32 status;
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status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
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if (!status)
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return IRQ_NONE;
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if (status & ERR_FATAL_IRQ)
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dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n",
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status);
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/* Ack the IRQ; status bits are RW1C */
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ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
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return IRQ_HANDLED;
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}
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static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
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{
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}
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static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
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{
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}
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static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
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{
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}
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static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
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.name = "Keystone-PCI-Legacy-IRQ",
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.irq_ack = ks_dw_pcie_ack_legacy_irq,
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.irq_mask = ks_dw_pcie_mask_legacy_irq,
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.irq_unmask = ks_dw_pcie_unmask_legacy_irq,
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};
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static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
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unsigned int irq, irq_hw_number_t hw_irq)
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{
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irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
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handle_level_irq);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
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.map = ks_dw_pcie_init_legacy_irq_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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/**
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* ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
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* registers
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*
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* Since modification of dbi_cs2 involves different clock domain, read the
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* status back to ensure the transition is complete.
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*/
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static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
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do {
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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} while (!(val & DBI_CS2_EN_VAL));
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}
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/**
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* ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
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*
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* Since modification of dbi_cs2 involves different clock domain, read the
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* status back to ensure the transition is complete.
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*/
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static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
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do {
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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} while (val & DBI_CS2_EN_VAL);
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}
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void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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u32 start = pp->mem->start, end = pp->mem->end;
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int i, tr_size;
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u32 val;
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/* Disable BARs for inbound access */
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ks_dw_pcie_set_dbi_mode(ks_pcie);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
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ks_dw_pcie_clear_dbi_mode(ks_pcie);
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/* Set outbound translation size per window division */
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ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
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tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
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/* Using Direct 1:1 mapping of RC <-> PCI memory space */
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for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
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ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
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ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
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start += tr_size;
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}
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/* Enable OB translation */
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
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}
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/**
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* ks_pcie_cfg_setup() - Set up configuration space address for a device
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*
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* @ks_pcie: ptr to keystone_pcie structure
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* @bus: Bus number the device is residing on
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* @devfn: device, function number info
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*
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* Forms and returns the address of configuration space mapped in PCIESS
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* address space 0. Also configures CFG_SETUP for remote configuration space
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* access.
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*
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* The address space has two regions to access configuration - local and remote.
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* We access local region for bus 0 (as RC is attached on bus 0) and remote
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* region for others with TYPE 1 access when bus > 1. As for device on bus = 1,
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* we will do TYPE 0 access as it will be on our secondary bus (logical).
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* CFG_SETUP is needed only for remote configuration access.
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*/
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static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
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unsigned int devfn)
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{
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u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
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struct dw_pcie *pci = ks_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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u32 regval;
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if (bus == 0)
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return pci->dbi_base;
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regval = (bus << 16) | (device << 8) | function;
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/*
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* Since Bus#1 will be a virtual bus, we need to have TYPE0
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* access only.
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* TYPE 1
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*/
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if (bus != 1)
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regval |= BIT(24);
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ks_dw_app_writel(ks_pcie, CFG_SETUP, regval);
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return pp->va_cfg0_base;
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}
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int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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u8 bus_num = bus->number;
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void __iomem *addr;
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addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
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return dw_pcie_read(addr + where, size, val);
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}
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int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 val)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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u8 bus_num = bus->number;
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void __iomem *addr;
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addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
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return dw_pcie_write(addr + where, size, val);
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}
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/**
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* ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
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*
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* This sets BAR0 to enable inbound access for MSI_IRQ register
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*/
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void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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/* Configure and set up BAR0 */
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ks_dw_pcie_set_dbi_mode(ks_pcie);
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/* Enable BAR0 */
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
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ks_dw_pcie_clear_dbi_mode(ks_pcie);
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/*
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* For BAR0, just setting bus address for inbound writes (MSI) should
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* be sufficient. Use physical address to avoid any conflicts.
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*/
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dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
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}
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/**
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* ks_dw_pcie_link_up() - Check if link up
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*/
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int ks_dw_pcie_link_up(struct dw_pcie *pci)
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{
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u32 val;
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val = dw_pcie_readl_dbi(pci, DEBUG0);
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return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
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}
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void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
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{
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u32 val;
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/* Disable Link training */
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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val &= ~LTSSM_EN_VAL;
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ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
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/* Initiate Link Training */
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val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
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ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
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}
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/**
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* ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
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*
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* Ioremap the register resources, initialize legacy irq domain
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* and call dw_pcie_v3_65_host_init() API to initialize the Keystone
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* PCI host controller.
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*/
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int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
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struct device_node *msi_intc_np)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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struct device *dev = pci->dev;
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struct platform_device *pdev = to_platform_device(dev);
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struct resource *res;
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/* Index 0 is the config reg. space address */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
|
|
if (IS_ERR(pci->dbi_base))
|
|
return PTR_ERR(pci->dbi_base);
|
|
|
|
/*
|
|
* We set these same and is used in pcie rd/wr_other_conf
|
|
* functions
|
|
*/
|
|
pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
|
|
pp->va_cfg1_base = pp->va_cfg0_base;
|
|
|
|
/* Index 1 is the application reg. space address */
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(ks_pcie->va_app_base))
|
|
return PTR_ERR(ks_pcie->va_app_base);
|
|
|
|
ks_pcie->app = *res;
|
|
|
|
/* Create legacy IRQ domain */
|
|
ks_pcie->legacy_irq_domain =
|
|
irq_domain_add_linear(ks_pcie->legacy_intc_np,
|
|
PCI_NUM_INTX,
|
|
&ks_dw_pcie_legacy_irq_domain_ops,
|
|
NULL);
|
|
if (!ks_pcie->legacy_irq_domain) {
|
|
dev_err(dev, "Failed to add irq domain for legacy irqs\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return dw_pcie_host_init(pp);
|
|
}
|