603 lines
16 KiB
C
603 lines
16 KiB
C
/*
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* Copyright (C) 2012 Texas Instruments
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kfifo.h>
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#include "tilcdc_drv.h"
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#include "tilcdc_regs.h"
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struct tilcdc_crtc {
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struct drm_crtc base;
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const struct tilcdc_panel_info *info;
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uint32_t dirty;
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dma_addr_t start, end;
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struct drm_pending_vblank_event *event;
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int dpms;
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wait_queue_head_t frame_done_wq;
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bool frame_done;
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/* fb currently set to scanout 0/1: */
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struct drm_framebuffer *scanout[2];
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/* for deferred fb unref's: */
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DECLARE_KFIFO_PTR(unref_fifo, struct drm_framebuffer *);
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struct work_struct work;
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};
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#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
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static void unref_worker(struct work_struct *work)
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{
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struct tilcdc_crtc *tilcdc_crtc = container_of(work, struct tilcdc_crtc, work);
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struct drm_device *dev = tilcdc_crtc->base.dev;
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struct drm_framebuffer *fb;
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mutex_lock(&dev->mode_config.mutex);
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while (kfifo_get(&tilcdc_crtc->unref_fifo, &fb))
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drm_framebuffer_unreference(fb);
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mutex_unlock(&dev->mode_config.mutex);
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}
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static void set_scanout(struct drm_crtc *crtc, int n)
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{
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static const uint32_t base_reg[] = {
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LCDC_DMA_FB_BASE_ADDR_0_REG, LCDC_DMA_FB_BASE_ADDR_1_REG,
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};
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static const uint32_t ceil_reg[] = {
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LCDC_DMA_FB_CEILING_ADDR_0_REG, LCDC_DMA_FB_CEILING_ADDR_1_REG,
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};
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static const uint32_t stat[] = {
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LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1,
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};
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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pm_runtime_get_sync(dev->dev);
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tilcdc_write(dev, base_reg[n], tilcdc_crtc->start);
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tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end);
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if (tilcdc_crtc->scanout[n]) {
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if (kfifo_put(&tilcdc_crtc->unref_fifo,
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(const struct drm_framebuffer **)&tilcdc_crtc->scanout[n])) {
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struct tilcdc_drm_private *priv = dev->dev_private;
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queue_work(priv->wq, &tilcdc_crtc->work);
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} else {
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dev_err(dev->dev, "unref fifo full!\n");
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drm_framebuffer_unreference(tilcdc_crtc->scanout[n]);
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}
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}
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tilcdc_crtc->scanout[n] = crtc->fb;
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drm_framebuffer_reference(tilcdc_crtc->scanout[n]);
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tilcdc_crtc->dirty &= ~stat[n];
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pm_runtime_put_sync(dev->dev);
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}
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static void update_scanout(struct drm_crtc *crtc)
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{
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_framebuffer *fb = crtc->fb;
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struct drm_gem_cma_object *gem;
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unsigned int depth, bpp;
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drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
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gem = drm_fb_cma_get_gem_obj(fb, 0);
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tilcdc_crtc->start = gem->paddr + fb->offsets[0] +
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(crtc->y * fb->pitches[0]) + (crtc->x * bpp/8);
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tilcdc_crtc->end = tilcdc_crtc->start +
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(crtc->mode.vdisplay * fb->pitches[0]);
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if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) {
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/* already enabled, so just mark the frames that need
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* updating and they will be updated on vblank:
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*/
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tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1;
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drm_vblank_get(dev, 0);
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} else {
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/* not enabled yet, so update registers immediately: */
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set_scanout(crtc, 0);
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set_scanout(crtc, 1);
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}
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}
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static void start(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct tilcdc_drm_private *priv = dev->dev_private;
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if (priv->rev == 2) {
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tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
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msleep(1);
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tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
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msleep(1);
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}
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tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
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tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
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tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
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}
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static void stop(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
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}
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static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
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{
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON);
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drm_crtc_cleanup(crtc);
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WARN_ON(!kfifo_is_empty(&tilcdc_crtc->unref_fifo));
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kfifo_free(&tilcdc_crtc->unref_fifo);
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kfree(tilcdc_crtc);
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}
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static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_pending_vblank_event *event)
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{
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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if (tilcdc_crtc->event) {
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dev_err(dev->dev, "already pending page flip!\n");
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return -EBUSY;
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}
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crtc->fb = fb;
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tilcdc_crtc->event = event;
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update_scanout(crtc);
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return 0;
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}
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static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct tilcdc_drm_private *priv = dev->dev_private;
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/* we really only care about on or off: */
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if (mode != DRM_MODE_DPMS_ON)
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mode = DRM_MODE_DPMS_OFF;
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if (tilcdc_crtc->dpms == mode)
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return;
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tilcdc_crtc->dpms = mode;
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pm_runtime_get_sync(dev->dev);
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if (mode == DRM_MODE_DPMS_ON) {
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pm_runtime_forbid(dev->dev);
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start(crtc);
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} else {
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tilcdc_crtc->frame_done = false;
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stop(crtc);
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/* if necessary wait for framedone irq which will still come
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* before putting things to sleep..
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*/
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if (priv->rev == 2) {
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int ret = wait_event_timeout(
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tilcdc_crtc->frame_done_wq,
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tilcdc_crtc->frame_done,
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msecs_to_jiffies(50));
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if (ret == 0)
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dev_err(dev->dev, "timeout waiting for framedone\n");
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}
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pm_runtime_allow(dev->dev);
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}
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pm_runtime_put_sync(dev->dev);
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}
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static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
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{
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tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
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}
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static void tilcdc_crtc_commit(struct drm_crtc *crtc)
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{
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tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
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}
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static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct tilcdc_drm_private *priv = dev->dev_private;
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const struct tilcdc_panel_info *info = tilcdc_crtc->info;
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uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
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int ret;
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ret = tilcdc_crtc_mode_valid(crtc, mode);
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if (WARN_ON(ret))
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return ret;
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if (WARN_ON(!info))
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return -EINVAL;
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pm_runtime_get_sync(dev->dev);
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/* Configure the Burst Size and fifo threshold of DMA: */
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reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
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switch (info->dma_burst_sz) {
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case 1:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
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break;
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case 2:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
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break;
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case 4:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
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break;
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case 8:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
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break;
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case 16:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
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break;
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default:
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return -EINVAL;
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}
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reg |= (info->fifo_th << 8);
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tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
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/* Configure timings: */
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hbp = mode->htotal - mode->hsync_end;
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hfp = mode->hsync_start - mode->hdisplay;
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hsw = mode->hsync_end - mode->hsync_start;
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vbp = mode->vtotal - mode->vsync_end;
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vfp = mode->vsync_start - mode->vdisplay;
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vsw = mode->vsync_end - mode->vsync_start;
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DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
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mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
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/* Configure the AC Bias Period and Number of Transitions per Interrupt: */
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reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
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reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
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LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
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if (priv->rev == 2) {
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reg |= (hfp & 0x300) >> 8;
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reg |= (hbp & 0x300) >> 4;
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reg |= (hsw & 0x3c0) << 21;
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}
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tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
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reg = (((mode->hdisplay >> 4) - 1) << 4) |
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((hbp & 0xff) << 24) |
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((hfp & 0xff) << 16) |
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((hsw & 0x3f) << 10);
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if (priv->rev == 2)
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reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
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tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
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reg = ((mode->vdisplay - 1) & 0x3ff) |
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((vbp & 0xff) << 24) |
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((vfp & 0xff) << 16) |
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((vsw & 0x3f) << 10);
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tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
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/* Configure display type: */
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reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
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~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
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LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
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reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
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if (info->tft_alt_mode)
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reg |= LCDC_TFT_ALT_ENABLE;
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if (priv->rev == 2) {
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unsigned int depth, bpp;
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drm_fb_get_bpp_depth(crtc->fb->pixel_format, &depth, &bpp);
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switch (bpp) {
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case 16:
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break;
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case 32:
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reg |= LCDC_V2_TFT_24BPP_UNPACK;
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/* fallthrough */
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case 24:
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reg |= LCDC_V2_TFT_24BPP_MODE;
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break;
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default:
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dev_err(dev->dev, "invalid pixel format\n");
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return -EINVAL;
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}
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}
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reg |= info->fdd < 12;
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tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
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if (info->invert_pxl_clk)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
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if (info->sync_ctrl)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
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if (info->sync_edge)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
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if (info->raster_order)
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tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
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else
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tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
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update_scanout(crtc);
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tilcdc_crtc_update_clk(crtc);
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pm_runtime_put_sync(dev->dev);
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return 0;
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}
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static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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update_scanout(crtc);
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return 0;
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}
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static void tilcdc_crtc_load_lut(struct drm_crtc *crtc)
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{
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}
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static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
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.destroy = tilcdc_crtc_destroy,
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.set_config = drm_crtc_helper_set_config,
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.page_flip = tilcdc_crtc_page_flip,
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};
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static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
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.dpms = tilcdc_crtc_dpms,
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.mode_fixup = tilcdc_crtc_mode_fixup,
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.prepare = tilcdc_crtc_prepare,
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.commit = tilcdc_crtc_commit,
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.mode_set = tilcdc_crtc_mode_set,
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.mode_set_base = tilcdc_crtc_mode_set_base,
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.load_lut = tilcdc_crtc_load_lut,
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};
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int tilcdc_crtc_max_width(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct tilcdc_drm_private *priv = dev->dev_private;
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int max_width = 0;
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if (priv->rev == 1)
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max_width = 1024;
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else if (priv->rev == 2)
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max_width = 2048;
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return max_width;
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}
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int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
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{
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struct tilcdc_drm_private *priv = crtc->dev->dev_private;
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unsigned int bandwidth;
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if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
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return MODE_VIRTUAL_X;
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/* width must be multiple of 16 */
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if (mode->hdisplay & 0xf)
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return MODE_VIRTUAL_X;
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if (mode->vdisplay > 2048)
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return MODE_VIRTUAL_Y;
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/* filter out modes that would require too much memory bandwidth: */
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bandwidth = mode->hdisplay * mode->vdisplay * drm_mode_vrefresh(mode);
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if (bandwidth > priv->max_bandwidth)
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return MODE_BAD;
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return MODE_OK;
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}
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void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
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const struct tilcdc_panel_info *info)
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{
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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tilcdc_crtc->info = info;
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}
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void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
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{
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct tilcdc_drm_private *priv = dev->dev_private;
|
|
int dpms = tilcdc_crtc->dpms;
|
|
unsigned int lcd_clk, div;
|
|
int ret;
|
|
|
|
pm_runtime_get_sync(dev->dev);
|
|
|
|
if (dpms == DRM_MODE_DPMS_ON)
|
|
tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
|
|
|
|
/* in raster mode, minimum divisor is 2: */
|
|
ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2);
|
|
if (ret) {
|
|
dev_err(dev->dev, "failed to set display clock rate to: %d\n",
|
|
crtc->mode.clock);
|
|
goto out;
|
|
}
|
|
|
|
lcd_clk = clk_get_rate(priv->clk);
|
|
div = lcd_clk / (crtc->mode.clock * 1000);
|
|
|
|
DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div);
|
|
DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk));
|
|
|
|
/* Configure the LCD clock divisor. */
|
|
tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) |
|
|
LCDC_RASTER_MODE);
|
|
|
|
if (priv->rev == 2)
|
|
tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
|
|
LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
|
|
LCDC_V2_CORE_CLK_EN);
|
|
|
|
if (dpms == DRM_MODE_DPMS_ON)
|
|
tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
|
|
|
|
out:
|
|
pm_runtime_put_sync(dev->dev);
|
|
}
|
|
|
|
irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
|
|
{
|
|
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
|
|
struct drm_device *dev = crtc->dev;
|
|
struct tilcdc_drm_private *priv = dev->dev_private;
|
|
uint32_t stat = tilcdc_read_irqstatus(dev);
|
|
|
|
if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) {
|
|
stop(crtc);
|
|
dev_err(dev->dev, "error: %08x\n", stat);
|
|
tilcdc_clear_irqstatus(dev, stat);
|
|
start(crtc);
|
|
} else if (stat & LCDC_PL_LOAD_DONE) {
|
|
tilcdc_clear_irqstatus(dev, stat);
|
|
} else {
|
|
struct drm_pending_vblank_event *event;
|
|
unsigned long flags;
|
|
uint32_t dirty = tilcdc_crtc->dirty & stat;
|
|
|
|
tilcdc_clear_irqstatus(dev, stat);
|
|
|
|
if (dirty & LCDC_END_OF_FRAME0)
|
|
set_scanout(crtc, 0);
|
|
|
|
if (dirty & LCDC_END_OF_FRAME1)
|
|
set_scanout(crtc, 1);
|
|
|
|
drm_handle_vblank(dev, 0);
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
event = tilcdc_crtc->event;
|
|
tilcdc_crtc->event = NULL;
|
|
if (event)
|
|
drm_send_vblank_event(dev, 0, event);
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
if (dirty && !tilcdc_crtc->dirty)
|
|
drm_vblank_put(dev, 0);
|
|
}
|
|
|
|
if (priv->rev == 2) {
|
|
if (stat & LCDC_FRAME_DONE) {
|
|
tilcdc_crtc->frame_done = true;
|
|
wake_up(&tilcdc_crtc->frame_done_wq);
|
|
}
|
|
tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
|
|
{
|
|
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
|
|
struct drm_pending_vblank_event *event;
|
|
struct drm_device *dev = crtc->dev;
|
|
unsigned long flags;
|
|
|
|
/* Destroy the pending vertical blanking event associated with the
|
|
* pending page flip, if any, and disable vertical blanking interrupts.
|
|
*/
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
event = tilcdc_crtc->event;
|
|
if (event && event->base.file_priv == file) {
|
|
tilcdc_crtc->event = NULL;
|
|
event->base.destroy(&event->base);
|
|
drm_vblank_put(dev, 0);
|
|
}
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
}
|
|
|
|
struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
|
|
{
|
|
struct tilcdc_crtc *tilcdc_crtc;
|
|
struct drm_crtc *crtc;
|
|
int ret;
|
|
|
|
tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL);
|
|
if (!tilcdc_crtc) {
|
|
dev_err(dev->dev, "allocation failed\n");
|
|
return NULL;
|
|
}
|
|
|
|
crtc = &tilcdc_crtc->base;
|
|
|
|
tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
|
|
init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
|
|
|
|
ret = kfifo_alloc(&tilcdc_crtc->unref_fifo, 16, GFP_KERNEL);
|
|
if (ret) {
|
|
dev_err(dev->dev, "could not allocate unref FIFO\n");
|
|
goto fail;
|
|
}
|
|
|
|
INIT_WORK(&tilcdc_crtc->work, unref_worker);
|
|
|
|
ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
|
|
if (ret < 0)
|
|
goto fail;
|
|
|
|
drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
|
|
|
|
return crtc;
|
|
|
|
fail:
|
|
tilcdc_crtc_destroy(crtc);
|
|
return NULL;
|
|
}
|