212 lines
6.3 KiB
C
212 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2015 Nikolay Martynov <mar.kolya@gmail.com>
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* Copyright (C) 2015 John Crispin <john@phrozen.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <asm/mipsregs.h>
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#include <asm/smp-ops.h>
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#include <asm/mips-cps.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/mt7621.h>
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#include <pinmux.h>
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#include "common.h"
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#define MT7621_GPIO_MODE_UART1 1
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#define MT7621_GPIO_MODE_I2C 2
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#define MT7621_GPIO_MODE_UART3_MASK 0x3
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#define MT7621_GPIO_MODE_UART3_SHIFT 3
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#define MT7621_GPIO_MODE_UART3_GPIO 1
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#define MT7621_GPIO_MODE_UART2_MASK 0x3
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#define MT7621_GPIO_MODE_UART2_SHIFT 5
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#define MT7621_GPIO_MODE_UART2_GPIO 1
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#define MT7621_GPIO_MODE_JTAG 7
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#define MT7621_GPIO_MODE_WDT_MASK 0x3
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#define MT7621_GPIO_MODE_WDT_SHIFT 8
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#define MT7621_GPIO_MODE_WDT_GPIO 1
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#define MT7621_GPIO_MODE_PCIE_RST 0
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#define MT7621_GPIO_MODE_PCIE_REF 2
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#define MT7621_GPIO_MODE_PCIE_MASK 0x3
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#define MT7621_GPIO_MODE_PCIE_SHIFT 10
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#define MT7621_GPIO_MODE_PCIE_GPIO 1
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#define MT7621_GPIO_MODE_MDIO_MASK 0x3
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#define MT7621_GPIO_MODE_MDIO_SHIFT 12
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#define MT7621_GPIO_MODE_MDIO_GPIO 1
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#define MT7621_GPIO_MODE_RGMII1 14
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#define MT7621_GPIO_MODE_RGMII2 15
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#define MT7621_GPIO_MODE_SPI_MASK 0x3
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#define MT7621_GPIO_MODE_SPI_SHIFT 16
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#define MT7621_GPIO_MODE_SPI_GPIO 1
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#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
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#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
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#define MT7621_GPIO_MODE_SDHCI_GPIO 1
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static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
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static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
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static struct rt2880_pmx_func uart3_grp[] = {
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FUNC("uart3", 0, 5, 4),
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FUNC("i2s", 2, 5, 4),
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FUNC("spdif3", 3, 5, 4),
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};
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static struct rt2880_pmx_func uart2_grp[] = {
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FUNC("uart2", 0, 9, 4),
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FUNC("pcm", 2, 9, 4),
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FUNC("spdif2", 3, 9, 4),
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};
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static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
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static struct rt2880_pmx_func wdt_grp[] = {
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FUNC("wdt rst", 0, 18, 1),
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FUNC("wdt refclk", 2, 18, 1),
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};
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static struct rt2880_pmx_func pcie_rst_grp[] = {
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FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
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FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
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};
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static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
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static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
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static struct rt2880_pmx_func spi_grp[] = {
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FUNC("spi", 0, 34, 7),
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FUNC("nand1", 2, 34, 7),
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};
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static struct rt2880_pmx_func sdhci_grp[] = {
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FUNC("sdhci", 0, 41, 8),
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FUNC("nand2", 2, 41, 8),
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};
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static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
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static struct rt2880_pmx_group mt7621_pinmux_data[] = {
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GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
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GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
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GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
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MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
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GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
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MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
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GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
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GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
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MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
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GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
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MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
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GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
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MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
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GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
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GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
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MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
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GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
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MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
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GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
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{ 0 }
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};
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phys_addr_t mips_cpc_default_phys_base(void)
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{
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panic("Cannot detect cpc address");
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}
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
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rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
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if (!rt_sysc_membase || !rt_memc_membase)
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panic("Failed to remap core resources");
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}
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static void soc_dev_init(struct ralink_soc_info *soc_info, u32 rev)
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{
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struct soc_device *soc_dev;
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struct soc_device_attribute *soc_dev_attr;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return;
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soc_dev_attr->soc_id = "mt7621";
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soc_dev_attr->family = "Ralink";
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if (((rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK) == 1 &&
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(rev & CHIP_REV_ECO_MASK) == 1)
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soc_dev_attr->revision = "E2";
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else
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soc_dev_attr->revision = "E1";
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soc_dev_attr->data = soc_info;
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr);
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return;
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}
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}
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void prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
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unsigned char *name = NULL;
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u32 n0;
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u32 n1;
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u32 rev;
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/* Early detection of CMP support */
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mips_cm_probe();
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mips_cpc_probe();
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if (mips_cps_numiocu(0)) {
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/*
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* mips_cm_probe() wipes out bootloader
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* config for CM regions and we have to configure them
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* again. This SoC cannot talk to pamlbus devices
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* witout proper iocu region set up.
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*
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* FIXME: it would be better to do this with values
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* from DT, but we need this very early because
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* without this we cannot talk to pretty much anything
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* including serial.
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*/
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write_gcr_reg0_base(MT7621_PALMBUS_BASE);
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write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
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CM_GCR_REGn_MASK_CMTGT_IOCU0);
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__sync();
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}
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
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name = "MT7621";
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soc_info->compatible = "mtk,mt7621-soc";
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} else {
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panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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}
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ralink_soc = MT762X_SOC_MT7621AT;
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rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"MediaTek %s ver:%u eco:%u",
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name,
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(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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(rev & CHIP_REV_ECO_MASK));
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soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
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soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
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soc_info->mem_base = MT7621_DRAM_BASE;
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rt2880_pinmux_data = mt7621_pinmux_data;
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soc_dev_init(soc_info, rev);
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if (!register_cps_smp_ops())
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return;
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if (!register_cmp_smp_ops())
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return;
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if (!register_vsmp_smp_ops())
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return;
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}
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