1793 lines
45 KiB
C
1793 lines
45 KiB
C
/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Derived from "arch/m68k/kernel/ptrace.c"
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* Copyright (C) 1994 by Hamish Macdonald
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* Taken from linux/kernel/ptrace.c and modified for M680x0.
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* linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
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*
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* Modified by Cort Dougan (cort@hq.fsmlabs.com)
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* and Paul Mackerras (paulus@samba.org).
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file README.legal in the main directory of
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* this archive for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/errno.h>
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#include <linux/ptrace.h>
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#include <linux/regset.h>
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#include <linux/tracehook.h>
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#include <linux/elf.h>
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#include <linux/user.h>
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#include <linux/security.h>
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#include <linux/signal.h>
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#include <linux/seccomp.h>
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#include <linux/audit.h>
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#include <trace/syscall.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/perf_event.h>
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#include <asm/uaccess.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/switch_to.h>
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#define CREATE_TRACE_POINTS
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#include <trace/events/syscalls.h>
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/*
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* The parameter save area on the stack is used to store arguments being passed
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* to callee function and is located at fixed offset from stack pointer.
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*/
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#ifdef CONFIG_PPC32
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#define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
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#else /* CONFIG_PPC32 */
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#define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
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#endif
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struct pt_regs_offset {
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const char *name;
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int offset;
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};
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#define STR(s) #s /* convert to string */
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#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
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#define GPR_OFFSET_NAME(num) \
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{.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
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#define REG_OFFSET_END {.name = NULL, .offset = 0}
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static const struct pt_regs_offset regoffset_table[] = {
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GPR_OFFSET_NAME(0),
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GPR_OFFSET_NAME(1),
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GPR_OFFSET_NAME(2),
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GPR_OFFSET_NAME(3),
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GPR_OFFSET_NAME(4),
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GPR_OFFSET_NAME(5),
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GPR_OFFSET_NAME(6),
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GPR_OFFSET_NAME(7),
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GPR_OFFSET_NAME(8),
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GPR_OFFSET_NAME(9),
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GPR_OFFSET_NAME(10),
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GPR_OFFSET_NAME(11),
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GPR_OFFSET_NAME(12),
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GPR_OFFSET_NAME(13),
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GPR_OFFSET_NAME(14),
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GPR_OFFSET_NAME(15),
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GPR_OFFSET_NAME(16),
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GPR_OFFSET_NAME(17),
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GPR_OFFSET_NAME(18),
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GPR_OFFSET_NAME(19),
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GPR_OFFSET_NAME(20),
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GPR_OFFSET_NAME(21),
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GPR_OFFSET_NAME(22),
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GPR_OFFSET_NAME(23),
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GPR_OFFSET_NAME(24),
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GPR_OFFSET_NAME(25),
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GPR_OFFSET_NAME(26),
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GPR_OFFSET_NAME(27),
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GPR_OFFSET_NAME(28),
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GPR_OFFSET_NAME(29),
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GPR_OFFSET_NAME(30),
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GPR_OFFSET_NAME(31),
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REG_OFFSET_NAME(nip),
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REG_OFFSET_NAME(msr),
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REG_OFFSET_NAME(ctr),
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REG_OFFSET_NAME(link),
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REG_OFFSET_NAME(xer),
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REG_OFFSET_NAME(ccr),
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#ifdef CONFIG_PPC64
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REG_OFFSET_NAME(softe),
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#else
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REG_OFFSET_NAME(mq),
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#endif
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REG_OFFSET_NAME(trap),
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REG_OFFSET_NAME(dar),
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REG_OFFSET_NAME(dsisr),
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REG_OFFSET_END,
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};
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/**
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* regs_query_register_offset() - query register offset from its name
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* @name: the name of a register
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*
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* regs_query_register_offset() returns the offset of a register in struct
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* pt_regs from its name. If the name is invalid, this returns -EINVAL;
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*/
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int regs_query_register_offset(const char *name)
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{
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const struct pt_regs_offset *roff;
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for (roff = regoffset_table; roff->name != NULL; roff++)
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if (!strcmp(roff->name, name))
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return roff->offset;
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return -EINVAL;
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}
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/**
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* regs_query_register_name() - query register name from its offset
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* @offset: the offset of a register in struct pt_regs.
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*
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* regs_query_register_name() returns the name of a register from its
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* offset in struct pt_regs. If the @offset is invalid, this returns NULL;
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*/
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const char *regs_query_register_name(unsigned int offset)
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{
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const struct pt_regs_offset *roff;
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for (roff = regoffset_table; roff->name != NULL; roff++)
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if (roff->offset == offset)
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return roff->name;
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return NULL;
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}
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/*
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* does not yet catch signals sent when the child dies.
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* in exit.c or in signal.c.
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*/
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/*
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* Set of msr bits that gdb can change on behalf of a process.
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*/
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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#define MSR_DEBUGCHANGE 0
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#else
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#define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
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#endif
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/*
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* Max register writeable via put_reg
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*/
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#ifdef CONFIG_PPC32
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#define PT_MAX_PUT_REG PT_MQ
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#else
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#define PT_MAX_PUT_REG PT_CCR
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#endif
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static unsigned long get_user_msr(struct task_struct *task)
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{
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return task->thread.regs->msr | task->thread.fpexc_mode;
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}
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static int set_user_msr(struct task_struct *task, unsigned long msr)
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{
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task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
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task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
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return 0;
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}
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/*
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* We prevent mucking around with the reserved area of trap
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* which are used internally by the kernel.
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*/
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static int set_user_trap(struct task_struct *task, unsigned long trap)
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{
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task->thread.regs->trap = trap & 0xfff0;
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return 0;
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}
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/*
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* Get contents of register REGNO in task TASK.
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*/
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unsigned long ptrace_get_reg(struct task_struct *task, int regno)
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{
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if (task->thread.regs == NULL)
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return -EIO;
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if (regno == PT_MSR)
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return get_user_msr(task);
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if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long)))
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return ((unsigned long *)task->thread.regs)[regno];
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return -EIO;
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}
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/*
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* Write contents of register REGNO in task TASK.
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*/
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int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
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{
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if (task->thread.regs == NULL)
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return -EIO;
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if (regno == PT_MSR)
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return set_user_msr(task, data);
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if (regno == PT_TRAP)
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return set_user_trap(task, data);
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if (regno <= PT_MAX_PUT_REG) {
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((unsigned long *)task->thread.regs)[regno] = data;
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return 0;
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}
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return -EIO;
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}
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static int gpr_get(struct task_struct *target, const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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int i, ret;
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if (target->thread.regs == NULL)
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return -EIO;
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if (!FULL_REGS(target->thread.regs)) {
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/* We have a partial register set. Fill 14-31 with bogus values */
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for (i = 14; i < 32; i++)
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target->thread.regs->gpr[i] = NV_REG_POISON;
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}
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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target->thread.regs,
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0, offsetof(struct pt_regs, msr));
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if (!ret) {
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unsigned long msr = get_user_msr(target);
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
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offsetof(struct pt_regs, msr),
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offsetof(struct pt_regs, msr) +
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sizeof(msr));
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}
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BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
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offsetof(struct pt_regs, msr) + sizeof(long));
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if (!ret)
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&target->thread.regs->orig_gpr3,
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offsetof(struct pt_regs, orig_gpr3),
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sizeof(struct pt_regs));
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if (!ret)
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ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
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sizeof(struct pt_regs), -1);
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return ret;
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}
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static int gpr_set(struct task_struct *target, const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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unsigned long reg;
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int ret;
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if (target->thread.regs == NULL)
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return -EIO;
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CHECK_FULL_REGS(target->thread.regs);
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
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target->thread.regs,
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0, PT_MSR * sizeof(reg));
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if (!ret && count > 0) {
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
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PT_MSR * sizeof(reg),
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(PT_MSR + 1) * sizeof(reg));
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if (!ret)
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ret = set_user_msr(target, reg);
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}
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BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
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offsetof(struct pt_regs, msr) + sizeof(long));
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if (!ret)
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
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&target->thread.regs->orig_gpr3,
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PT_ORIG_R3 * sizeof(reg),
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(PT_MAX_PUT_REG + 1) * sizeof(reg));
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if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
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ret = user_regset_copyin_ignore(
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&pos, &count, &kbuf, &ubuf,
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(PT_MAX_PUT_REG + 1) * sizeof(reg),
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PT_TRAP * sizeof(reg));
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if (!ret && count > 0) {
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
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PT_TRAP * sizeof(reg),
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(PT_TRAP + 1) * sizeof(reg));
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if (!ret)
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ret = set_user_trap(target, reg);
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}
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if (!ret)
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ret = user_regset_copyin_ignore(
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&pos, &count, &kbuf, &ubuf,
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(PT_TRAP + 1) * sizeof(reg), -1);
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return ret;
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}
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static int fpr_get(struct task_struct *target, const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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#ifdef CONFIG_VSX
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double buf[33];
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int i;
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#endif
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flush_fp_to_thread(target);
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#ifdef CONFIG_VSX
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/* copy to local buffer then write that out */
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for (i = 0; i < 32 ; i++)
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buf[i] = target->thread.TS_FPR(i);
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memcpy(&buf[32], &target->thread.fpscr, sizeof(double));
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return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
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#else
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BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
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offsetof(struct thread_struct, TS_FPR(32)));
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return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&target->thread.fpr, 0, -1);
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#endif
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}
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static int fpr_set(struct task_struct *target, const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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#ifdef CONFIG_VSX
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double buf[33];
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int i;
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#endif
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flush_fp_to_thread(target);
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#ifdef CONFIG_VSX
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/* copy to local buffer then write that out */
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i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
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if (i)
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return i;
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for (i = 0; i < 32 ; i++)
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target->thread.TS_FPR(i) = buf[i];
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memcpy(&target->thread.fpscr, &buf[32], sizeof(double));
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return 0;
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#else
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BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
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offsetof(struct thread_struct, TS_FPR(32)));
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return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
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&target->thread.fpr, 0, -1);
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#endif
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}
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#ifdef CONFIG_ALTIVEC
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/*
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* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
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* The transfer totals 34 quadword. Quadwords 0-31 contain the
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* corresponding vector registers. Quadword 32 contains the vscr as the
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* last word (offset 12) within that quadword. Quadword 33 contains the
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* vrsave as the first word (offset 0) within the quadword.
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*
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* This definition of the VMX state is compatible with the current PPC32
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* ptrace interface. This allows signal handling and ptrace to use the
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* same structures. This also simplifies the implementation of a bi-arch
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* (combined (32- and 64-bit) gdb.
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*/
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static int vr_active(struct task_struct *target,
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const struct user_regset *regset)
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{
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flush_altivec_to_thread(target);
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return target->thread.used_vr ? regset->n : 0;
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}
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static int vr_get(struct task_struct *target, const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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int ret;
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flush_altivec_to_thread(target);
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BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
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offsetof(struct thread_struct, vr[32]));
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
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&target->thread.vr, 0,
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33 * sizeof(vector128));
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if (!ret) {
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/*
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* Copy out only the low-order word of vrsave.
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*/
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union {
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elf_vrreg_t reg;
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u32 word;
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} vrsave;
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memset(&vrsave, 0, sizeof(vrsave));
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vrsave.word = target->thread.vrsave;
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ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
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33 * sizeof(vector128), -1);
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}
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return ret;
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}
|
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|
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static int vr_set(struct task_struct *target, const struct user_regset *regset,
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unsigned int pos, unsigned int count,
|
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const void *kbuf, const void __user *ubuf)
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{
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int ret;
|
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|
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flush_altivec_to_thread(target);
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BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
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offsetof(struct thread_struct, vr[32]));
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
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&target->thread.vr, 0, 33 * sizeof(vector128));
|
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if (!ret && count > 0) {
|
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/*
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* We use only the first word of vrsave.
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*/
|
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union {
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elf_vrreg_t reg;
|
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u32 word;
|
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} vrsave;
|
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memset(&vrsave, 0, sizeof(vrsave));
|
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vrsave.word = target->thread.vrsave;
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ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
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33 * sizeof(vector128), -1);
|
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if (!ret)
|
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target->thread.vrsave = vrsave.word;
|
|
}
|
|
|
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return ret;
|
|
}
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
#ifdef CONFIG_VSX
|
|
/*
|
|
* Currently to set and and get all the vsx state, you need to call
|
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* the fp and VMX calls as well. This only get/sets the lower 32
|
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* 128bit VSX registers.
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*/
|
|
|
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static int vsr_active(struct task_struct *target,
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const struct user_regset *regset)
|
|
{
|
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flush_vsx_to_thread(target);
|
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return target->thread.used_vsr ? regset->n : 0;
|
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}
|
|
|
|
static int vsr_get(struct task_struct *target, const struct user_regset *regset,
|
|
unsigned int pos, unsigned int count,
|
|
void *kbuf, void __user *ubuf)
|
|
{
|
|
double buf[32];
|
|
int ret, i;
|
|
|
|
flush_vsx_to_thread(target);
|
|
|
|
for (i = 0; i < 32 ; i++)
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buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET];
|
|
ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
|
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buf, 0, 32 * sizeof(double));
|
|
|
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return ret;
|
|
}
|
|
|
|
static int vsr_set(struct task_struct *target, const struct user_regset *regset,
|
|
unsigned int pos, unsigned int count,
|
|
const void *kbuf, const void __user *ubuf)
|
|
{
|
|
double buf[32];
|
|
int ret,i;
|
|
|
|
flush_vsx_to_thread(target);
|
|
|
|
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
|
|
buf, 0, 32 * sizeof(double));
|
|
for (i = 0; i < 32 ; i++)
|
|
target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i];
|
|
|
|
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_VSX */
|
|
|
|
#ifdef CONFIG_SPE
|
|
|
|
/*
|
|
* For get_evrregs/set_evrregs functions 'data' has the following layout:
|
|
*
|
|
* struct {
|
|
* u32 evr[32];
|
|
* u64 acc;
|
|
* u32 spefscr;
|
|
* }
|
|
*/
|
|
|
|
static int evr_active(struct task_struct *target,
|
|
const struct user_regset *regset)
|
|
{
|
|
flush_spe_to_thread(target);
|
|
return target->thread.used_spe ? regset->n : 0;
|
|
}
|
|
|
|
static int evr_get(struct task_struct *target, const struct user_regset *regset,
|
|
unsigned int pos, unsigned int count,
|
|
void *kbuf, void __user *ubuf)
|
|
{
|
|
int ret;
|
|
|
|
flush_spe_to_thread(target);
|
|
|
|
ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
|
|
&target->thread.evr,
|
|
0, sizeof(target->thread.evr));
|
|
|
|
BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
|
|
offsetof(struct thread_struct, spefscr));
|
|
|
|
if (!ret)
|
|
ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
|
|
&target->thread.acc,
|
|
sizeof(target->thread.evr), -1);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int evr_set(struct task_struct *target, const struct user_regset *regset,
|
|
unsigned int pos, unsigned int count,
|
|
const void *kbuf, const void __user *ubuf)
|
|
{
|
|
int ret;
|
|
|
|
flush_spe_to_thread(target);
|
|
|
|
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
|
|
&target->thread.evr,
|
|
0, sizeof(target->thread.evr));
|
|
|
|
BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
|
|
offsetof(struct thread_struct, spefscr));
|
|
|
|
if (!ret)
|
|
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
|
|
&target->thread.acc,
|
|
sizeof(target->thread.evr), -1);
|
|
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_SPE */
|
|
|
|
|
|
/*
|
|
* These are our native regset flavors.
|
|
*/
|
|
enum powerpc_regset {
|
|
REGSET_GPR,
|
|
REGSET_FPR,
|
|
#ifdef CONFIG_ALTIVEC
|
|
REGSET_VMX,
|
|
#endif
|
|
#ifdef CONFIG_VSX
|
|
REGSET_VSX,
|
|
#endif
|
|
#ifdef CONFIG_SPE
|
|
REGSET_SPE,
|
|
#endif
|
|
};
|
|
|
|
static const struct user_regset native_regsets[] = {
|
|
[REGSET_GPR] = {
|
|
.core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
|
|
.size = sizeof(long), .align = sizeof(long),
|
|
.get = gpr_get, .set = gpr_set
|
|
},
|
|
[REGSET_FPR] = {
|
|
.core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
|
|
.size = sizeof(double), .align = sizeof(double),
|
|
.get = fpr_get, .set = fpr_set
|
|
},
|
|
#ifdef CONFIG_ALTIVEC
|
|
[REGSET_VMX] = {
|
|
.core_note_type = NT_PPC_VMX, .n = 34,
|
|
.size = sizeof(vector128), .align = sizeof(vector128),
|
|
.active = vr_active, .get = vr_get, .set = vr_set
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_VSX
|
|
[REGSET_VSX] = {
|
|
.core_note_type = NT_PPC_VSX, .n = 32,
|
|
.size = sizeof(double), .align = sizeof(double),
|
|
.active = vsr_active, .get = vsr_get, .set = vsr_set
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_SPE
|
|
[REGSET_SPE] = {
|
|
.n = 35,
|
|
.size = sizeof(u32), .align = sizeof(u32),
|
|
.active = evr_active, .get = evr_get, .set = evr_set
|
|
},
|
|
#endif
|
|
};
|
|
|
|
static const struct user_regset_view user_ppc_native_view = {
|
|
.name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
|
|
.regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
|
|
};
|
|
|
|
#ifdef CONFIG_PPC64
|
|
#include <linux/compat.h>
|
|
|
|
static int gpr32_get(struct task_struct *target,
|
|
const struct user_regset *regset,
|
|
unsigned int pos, unsigned int count,
|
|
void *kbuf, void __user *ubuf)
|
|
{
|
|
const unsigned long *regs = &target->thread.regs->gpr[0];
|
|
compat_ulong_t *k = kbuf;
|
|
compat_ulong_t __user *u = ubuf;
|
|
compat_ulong_t reg;
|
|
int i;
|
|
|
|
if (target->thread.regs == NULL)
|
|
return -EIO;
|
|
|
|
if (!FULL_REGS(target->thread.regs)) {
|
|
/* We have a partial register set. Fill 14-31 with bogus values */
|
|
for (i = 14; i < 32; i++)
|
|
target->thread.regs->gpr[i] = NV_REG_POISON;
|
|
}
|
|
|
|
pos /= sizeof(reg);
|
|
count /= sizeof(reg);
|
|
|
|
if (kbuf)
|
|
for (; count > 0 && pos < PT_MSR; --count)
|
|
*k++ = regs[pos++];
|
|
else
|
|
for (; count > 0 && pos < PT_MSR; --count)
|
|
if (__put_user((compat_ulong_t) regs[pos++], u++))
|
|
return -EFAULT;
|
|
|
|
if (count > 0 && pos == PT_MSR) {
|
|
reg = get_user_msr(target);
|
|
if (kbuf)
|
|
*k++ = reg;
|
|
else if (__put_user(reg, u++))
|
|
return -EFAULT;
|
|
++pos;
|
|
--count;
|
|
}
|
|
|
|
if (kbuf)
|
|
for (; count > 0 && pos < PT_REGS_COUNT; --count)
|
|
*k++ = regs[pos++];
|
|
else
|
|
for (; count > 0 && pos < PT_REGS_COUNT; --count)
|
|
if (__put_user((compat_ulong_t) regs[pos++], u++))
|
|
return -EFAULT;
|
|
|
|
kbuf = k;
|
|
ubuf = u;
|
|
pos *= sizeof(reg);
|
|
count *= sizeof(reg);
|
|
return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
|
|
PT_REGS_COUNT * sizeof(reg), -1);
|
|
}
|
|
|
|
static int gpr32_set(struct task_struct *target,
|
|
const struct user_regset *regset,
|
|
unsigned int pos, unsigned int count,
|
|
const void *kbuf, const void __user *ubuf)
|
|
{
|
|
unsigned long *regs = &target->thread.regs->gpr[0];
|
|
const compat_ulong_t *k = kbuf;
|
|
const compat_ulong_t __user *u = ubuf;
|
|
compat_ulong_t reg;
|
|
|
|
if (target->thread.regs == NULL)
|
|
return -EIO;
|
|
|
|
CHECK_FULL_REGS(target->thread.regs);
|
|
|
|
pos /= sizeof(reg);
|
|
count /= sizeof(reg);
|
|
|
|
if (kbuf)
|
|
for (; count > 0 && pos < PT_MSR; --count)
|
|
regs[pos++] = *k++;
|
|
else
|
|
for (; count > 0 && pos < PT_MSR; --count) {
|
|
if (__get_user(reg, u++))
|
|
return -EFAULT;
|
|
regs[pos++] = reg;
|
|
}
|
|
|
|
|
|
if (count > 0 && pos == PT_MSR) {
|
|
if (kbuf)
|
|
reg = *k++;
|
|
else if (__get_user(reg, u++))
|
|
return -EFAULT;
|
|
set_user_msr(target, reg);
|
|
++pos;
|
|
--count;
|
|
}
|
|
|
|
if (kbuf) {
|
|
for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
|
|
regs[pos++] = *k++;
|
|
for (; count > 0 && pos < PT_TRAP; --count, ++pos)
|
|
++k;
|
|
} else {
|
|
for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
|
|
if (__get_user(reg, u++))
|
|
return -EFAULT;
|
|
regs[pos++] = reg;
|
|
}
|
|
for (; count > 0 && pos < PT_TRAP; --count, ++pos)
|
|
if (__get_user(reg, u++))
|
|
return -EFAULT;
|
|
}
|
|
|
|
if (count > 0 && pos == PT_TRAP) {
|
|
if (kbuf)
|
|
reg = *k++;
|
|
else if (__get_user(reg, u++))
|
|
return -EFAULT;
|
|
set_user_trap(target, reg);
|
|
++pos;
|
|
--count;
|
|
}
|
|
|
|
kbuf = k;
|
|
ubuf = u;
|
|
pos *= sizeof(reg);
|
|
count *= sizeof(reg);
|
|
return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
|
|
(PT_TRAP + 1) * sizeof(reg), -1);
|
|
}
|
|
|
|
/*
|
|
* These are the regset flavors matching the CONFIG_PPC32 native set.
|
|
*/
|
|
static const struct user_regset compat_regsets[] = {
|
|
[REGSET_GPR] = {
|
|
.core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
|
|
.size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
|
|
.get = gpr32_get, .set = gpr32_set
|
|
},
|
|
[REGSET_FPR] = {
|
|
.core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
|
|
.size = sizeof(double), .align = sizeof(double),
|
|
.get = fpr_get, .set = fpr_set
|
|
},
|
|
#ifdef CONFIG_ALTIVEC
|
|
[REGSET_VMX] = {
|
|
.core_note_type = NT_PPC_VMX, .n = 34,
|
|
.size = sizeof(vector128), .align = sizeof(vector128),
|
|
.active = vr_active, .get = vr_get, .set = vr_set
|
|
},
|
|
#endif
|
|
#ifdef CONFIG_SPE
|
|
[REGSET_SPE] = {
|
|
.core_note_type = NT_PPC_SPE, .n = 35,
|
|
.size = sizeof(u32), .align = sizeof(u32),
|
|
.active = evr_active, .get = evr_get, .set = evr_set
|
|
},
|
|
#endif
|
|
};
|
|
|
|
static const struct user_regset_view user_ppc_compat_view = {
|
|
.name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
|
|
.regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
|
|
};
|
|
#endif /* CONFIG_PPC64 */
|
|
|
|
const struct user_regset_view *task_user_regset_view(struct task_struct *task)
|
|
{
|
|
#ifdef CONFIG_PPC64
|
|
if (test_tsk_thread_flag(task, TIF_32BIT))
|
|
return &user_ppc_compat_view;
|
|
#endif
|
|
return &user_ppc_native_view;
|
|
}
|
|
|
|
|
|
void user_enable_single_step(struct task_struct *task)
|
|
{
|
|
struct pt_regs *regs = task->thread.regs;
|
|
|
|
if (regs != NULL) {
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
task->thread.dbcr0 &= ~DBCR0_BT;
|
|
task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
|
|
regs->msr |= MSR_DE;
|
|
#else
|
|
regs->msr &= ~MSR_BE;
|
|
regs->msr |= MSR_SE;
|
|
#endif
|
|
}
|
|
set_tsk_thread_flag(task, TIF_SINGLESTEP);
|
|
}
|
|
|
|
void user_enable_block_step(struct task_struct *task)
|
|
{
|
|
struct pt_regs *regs = task->thread.regs;
|
|
|
|
if (regs != NULL) {
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
task->thread.dbcr0 &= ~DBCR0_IC;
|
|
task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
|
|
regs->msr |= MSR_DE;
|
|
#else
|
|
regs->msr &= ~MSR_SE;
|
|
regs->msr |= MSR_BE;
|
|
#endif
|
|
}
|
|
set_tsk_thread_flag(task, TIF_SINGLESTEP);
|
|
}
|
|
|
|
void user_disable_single_step(struct task_struct *task)
|
|
{
|
|
struct pt_regs *regs = task->thread.regs;
|
|
|
|
if (regs != NULL) {
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
/*
|
|
* The logic to disable single stepping should be as
|
|
* simple as turning off the Instruction Complete flag.
|
|
* And, after doing so, if all debug flags are off, turn
|
|
* off DBCR0(IDM) and MSR(DE) .... Torez
|
|
*/
|
|
task->thread.dbcr0 &= ~DBCR0_IC;
|
|
/*
|
|
* Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
|
|
*/
|
|
if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
|
|
task->thread.dbcr1)) {
|
|
/*
|
|
* All debug events were off.....
|
|
*/
|
|
task->thread.dbcr0 &= ~DBCR0_IDM;
|
|
regs->msr &= ~MSR_DE;
|
|
}
|
|
#else
|
|
regs->msr &= ~(MSR_SE | MSR_BE);
|
|
#endif
|
|
}
|
|
clear_tsk_thread_flag(task, TIF_SINGLESTEP);
|
|
}
|
|
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
|
void ptrace_triggered(struct perf_event *bp,
|
|
struct perf_sample_data *data, struct pt_regs *regs)
|
|
{
|
|
struct perf_event_attr attr;
|
|
|
|
/*
|
|
* Disable the breakpoint request here since ptrace has defined a
|
|
* one-shot behaviour for breakpoint exceptions in PPC64.
|
|
* The SIGTRAP signal is generated automatically for us in do_dabr().
|
|
* We don't have to do anything about that here
|
|
*/
|
|
attr = bp->attr;
|
|
attr.disabled = true;
|
|
modify_user_hw_breakpoint(bp, &attr);
|
|
}
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
|
|
|
int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
|
|
unsigned long data)
|
|
{
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
|
int ret;
|
|
struct thread_struct *thread = &(task->thread);
|
|
struct perf_event *bp;
|
|
struct perf_event_attr attr;
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
|
|
|
/* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
|
|
* For embedded processors we support one DAC and no IAC's at the
|
|
* moment.
|
|
*/
|
|
if (addr > 0)
|
|
return -EINVAL;
|
|
|
|
/* The bottom 3 bits in dabr are flags */
|
|
if ((data & ~0x7UL) >= TASK_SIZE)
|
|
return -EIO;
|
|
|
|
#ifndef CONFIG_PPC_ADV_DEBUG_REGS
|
|
/* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
|
|
* It was assumed, on previous implementations, that 3 bits were
|
|
* passed together with the data address, fitting the design of the
|
|
* DABR register, as follows:
|
|
*
|
|
* bit 0: Read flag
|
|
* bit 1: Write flag
|
|
* bit 2: Breakpoint translation
|
|
*
|
|
* Thus, we use them here as so.
|
|
*/
|
|
|
|
/* Ensure breakpoint translation bit is set */
|
|
if (data && !(data & DABR_TRANSLATION))
|
|
return -EIO;
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
|
if (ptrace_get_breakpoints(task) < 0)
|
|
return -ESRCH;
|
|
|
|
bp = thread->ptrace_bps[0];
|
|
if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
|
|
if (bp) {
|
|
unregister_hw_breakpoint(bp);
|
|
thread->ptrace_bps[0] = NULL;
|
|
}
|
|
ptrace_put_breakpoints(task);
|
|
return 0;
|
|
}
|
|
if (bp) {
|
|
attr = bp->attr;
|
|
attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
|
|
arch_bp_generic_fields(data &
|
|
(DABR_DATA_WRITE | DABR_DATA_READ),
|
|
&attr.bp_type);
|
|
|
|
/* Enable breakpoint */
|
|
attr.disabled = false;
|
|
|
|
ret = modify_user_hw_breakpoint(bp, &attr);
|
|
if (ret) {
|
|
ptrace_put_breakpoints(task);
|
|
return ret;
|
|
}
|
|
thread->ptrace_bps[0] = bp;
|
|
ptrace_put_breakpoints(task);
|
|
thread->dabr = data;
|
|
thread->dabrx = DABRX_ALL;
|
|
return 0;
|
|
}
|
|
|
|
/* Create a new breakpoint request if one doesn't exist already */
|
|
hw_breakpoint_init(&attr);
|
|
attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
|
|
arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ),
|
|
&attr.bp_type);
|
|
|
|
thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
|
|
ptrace_triggered, NULL, task);
|
|
if (IS_ERR(bp)) {
|
|
thread->ptrace_bps[0] = NULL;
|
|
ptrace_put_breakpoints(task);
|
|
return PTR_ERR(bp);
|
|
}
|
|
|
|
ptrace_put_breakpoints(task);
|
|
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
|
|
|
/* Move contents to the DABR register */
|
|
task->thread.dabr = data;
|
|
task->thread.dabrx = DABRX_ALL;
|
|
#else /* CONFIG_PPC_ADV_DEBUG_REGS */
|
|
/* As described above, it was assumed 3 bits were passed with the data
|
|
* address, but we will assume only the mode bits will be passed
|
|
* as to not cause alignment restrictions for DAC-based processors.
|
|
*/
|
|
|
|
/* DAC's hold the whole address without any mode flags */
|
|
task->thread.dac1 = data & ~0x3UL;
|
|
|
|
if (task->thread.dac1 == 0) {
|
|
dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
|
|
if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
|
|
task->thread.dbcr1)) {
|
|
task->thread.regs->msr &= ~MSR_DE;
|
|
task->thread.dbcr0 &= ~DBCR0_IDM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Read or Write bits must be set */
|
|
|
|
if (!(data & 0x3UL))
|
|
return -EINVAL;
|
|
|
|
/* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
|
|
register */
|
|
task->thread.dbcr0 |= DBCR0_IDM;
|
|
|
|
/* Check for write and read flags and set DBCR0
|
|
accordingly */
|
|
dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
|
|
if (data & 0x1UL)
|
|
dbcr_dac(task) |= DBCR_DAC1R;
|
|
if (data & 0x2UL)
|
|
dbcr_dac(task) |= DBCR_DAC1W;
|
|
task->thread.regs->msr |= MSR_DE;
|
|
#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Called by kernel/ptrace.c when detaching..
|
|
*
|
|
* Make sure single step bits etc are not set.
|
|
*/
|
|
void ptrace_disable(struct task_struct *child)
|
|
{
|
|
/* make sure the single step bit is not set. */
|
|
user_disable_single_step(child);
|
|
}
|
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
static long set_instruction_bp(struct task_struct *child,
|
|
struct ppc_hw_breakpoint *bp_info)
|
|
{
|
|
int slot;
|
|
int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
|
|
int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
|
|
int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
|
|
int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
|
|
|
|
if (dbcr_iac_range(child) & DBCR_IAC12MODE)
|
|
slot2_in_use = 1;
|
|
if (dbcr_iac_range(child) & DBCR_IAC34MODE)
|
|
slot4_in_use = 1;
|
|
|
|
if (bp_info->addr >= TASK_SIZE)
|
|
return -EIO;
|
|
|
|
if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
|
|
|
|
/* Make sure range is valid. */
|
|
if (bp_info->addr2 >= TASK_SIZE)
|
|
return -EIO;
|
|
|
|
/* We need a pair of IAC regsisters */
|
|
if ((!slot1_in_use) && (!slot2_in_use)) {
|
|
slot = 1;
|
|
child->thread.iac1 = bp_info->addr;
|
|
child->thread.iac2 = bp_info->addr2;
|
|
child->thread.dbcr0 |= DBCR0_IAC1;
|
|
if (bp_info->addr_mode ==
|
|
PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
|
|
dbcr_iac_range(child) |= DBCR_IAC12X;
|
|
else
|
|
dbcr_iac_range(child) |= DBCR_IAC12I;
|
|
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
|
} else if ((!slot3_in_use) && (!slot4_in_use)) {
|
|
slot = 3;
|
|
child->thread.iac3 = bp_info->addr;
|
|
child->thread.iac4 = bp_info->addr2;
|
|
child->thread.dbcr0 |= DBCR0_IAC3;
|
|
if (bp_info->addr_mode ==
|
|
PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
|
|
dbcr_iac_range(child) |= DBCR_IAC34X;
|
|
else
|
|
dbcr_iac_range(child) |= DBCR_IAC34I;
|
|
#endif
|
|
} else
|
|
return -ENOSPC;
|
|
} else {
|
|
/* We only need one. If possible leave a pair free in
|
|
* case a range is needed later
|
|
*/
|
|
if (!slot1_in_use) {
|
|
/*
|
|
* Don't use iac1 if iac1-iac2 are free and either
|
|
* iac3 or iac4 (but not both) are free
|
|
*/
|
|
if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
|
|
slot = 1;
|
|
child->thread.iac1 = bp_info->addr;
|
|
child->thread.dbcr0 |= DBCR0_IAC1;
|
|
goto out;
|
|
}
|
|
}
|
|
if (!slot2_in_use) {
|
|
slot = 2;
|
|
child->thread.iac2 = bp_info->addr;
|
|
child->thread.dbcr0 |= DBCR0_IAC2;
|
|
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
|
} else if (!slot3_in_use) {
|
|
slot = 3;
|
|
child->thread.iac3 = bp_info->addr;
|
|
child->thread.dbcr0 |= DBCR0_IAC3;
|
|
} else if (!slot4_in_use) {
|
|
slot = 4;
|
|
child->thread.iac4 = bp_info->addr;
|
|
child->thread.dbcr0 |= DBCR0_IAC4;
|
|
#endif
|
|
} else
|
|
return -ENOSPC;
|
|
}
|
|
out:
|
|
child->thread.dbcr0 |= DBCR0_IDM;
|
|
child->thread.regs->msr |= MSR_DE;
|
|
|
|
return slot;
|
|
}
|
|
|
|
static int del_instruction_bp(struct task_struct *child, int slot)
|
|
{
|
|
switch (slot) {
|
|
case 1:
|
|
if ((child->thread.dbcr0 & DBCR0_IAC1) == 0)
|
|
return -ENOENT;
|
|
|
|
if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
|
|
/* address range - clear slots 1 & 2 */
|
|
child->thread.iac2 = 0;
|
|
dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
|
|
}
|
|
child->thread.iac1 = 0;
|
|
child->thread.dbcr0 &= ~DBCR0_IAC1;
|
|
break;
|
|
case 2:
|
|
if ((child->thread.dbcr0 & DBCR0_IAC2) == 0)
|
|
return -ENOENT;
|
|
|
|
if (dbcr_iac_range(child) & DBCR_IAC12MODE)
|
|
/* used in a range */
|
|
return -EINVAL;
|
|
child->thread.iac2 = 0;
|
|
child->thread.dbcr0 &= ~DBCR0_IAC2;
|
|
break;
|
|
#if CONFIG_PPC_ADV_DEBUG_IACS > 2
|
|
case 3:
|
|
if ((child->thread.dbcr0 & DBCR0_IAC3) == 0)
|
|
return -ENOENT;
|
|
|
|
if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
|
|
/* address range - clear slots 3 & 4 */
|
|
child->thread.iac4 = 0;
|
|
dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
|
|
}
|
|
child->thread.iac3 = 0;
|
|
child->thread.dbcr0 &= ~DBCR0_IAC3;
|
|
break;
|
|
case 4:
|
|
if ((child->thread.dbcr0 & DBCR0_IAC4) == 0)
|
|
return -ENOENT;
|
|
|
|
if (dbcr_iac_range(child) & DBCR_IAC34MODE)
|
|
/* Used in a range */
|
|
return -EINVAL;
|
|
child->thread.iac4 = 0;
|
|
child->thread.dbcr0 &= ~DBCR0_IAC4;
|
|
break;
|
|
#endif
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
|
|
{
|
|
int byte_enable =
|
|
(bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
|
|
& 0xf;
|
|
int condition_mode =
|
|
bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
|
|
int slot;
|
|
|
|
if (byte_enable && (condition_mode == 0))
|
|
return -EINVAL;
|
|
|
|
if (bp_info->addr >= TASK_SIZE)
|
|
return -EIO;
|
|
|
|
if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
|
|
slot = 1;
|
|
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
|
|
dbcr_dac(child) |= DBCR_DAC1R;
|
|
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
|
dbcr_dac(child) |= DBCR_DAC1W;
|
|
child->thread.dac1 = (unsigned long)bp_info->addr;
|
|
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
|
if (byte_enable) {
|
|
child->thread.dvc1 =
|
|
(unsigned long)bp_info->condition_value;
|
|
child->thread.dbcr2 |=
|
|
((byte_enable << DBCR2_DVC1BE_SHIFT) |
|
|
(condition_mode << DBCR2_DVC1M_SHIFT));
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
|
} else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
|
|
/* Both dac1 and dac2 are part of a range */
|
|
return -ENOSPC;
|
|
#endif
|
|
} else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
|
|
slot = 2;
|
|
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
|
|
dbcr_dac(child) |= DBCR_DAC2R;
|
|
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
|
dbcr_dac(child) |= DBCR_DAC2W;
|
|
child->thread.dac2 = (unsigned long)bp_info->addr;
|
|
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
|
if (byte_enable) {
|
|
child->thread.dvc2 =
|
|
(unsigned long)bp_info->condition_value;
|
|
child->thread.dbcr2 |=
|
|
((byte_enable << DBCR2_DVC2BE_SHIFT) |
|
|
(condition_mode << DBCR2_DVC2M_SHIFT));
|
|
}
|
|
#endif
|
|
} else
|
|
return -ENOSPC;
|
|
child->thread.dbcr0 |= DBCR0_IDM;
|
|
child->thread.regs->msr |= MSR_DE;
|
|
|
|
return slot + 4;
|
|
}
|
|
|
|
static int del_dac(struct task_struct *child, int slot)
|
|
{
|
|
if (slot == 1) {
|
|
if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
|
|
return -ENOENT;
|
|
|
|
child->thread.dac1 = 0;
|
|
dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
|
if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
|
|
child->thread.dac2 = 0;
|
|
child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
|
|
}
|
|
child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
|
|
#endif
|
|
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
|
child->thread.dvc1 = 0;
|
|
#endif
|
|
} else if (slot == 2) {
|
|
if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
|
|
return -ENOENT;
|
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
|
if (child->thread.dbcr2 & DBCR2_DAC12MODE)
|
|
/* Part of a range */
|
|
return -EINVAL;
|
|
child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
|
|
#endif
|
|
#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
|
|
child->thread.dvc2 = 0;
|
|
#endif
|
|
child->thread.dac2 = 0;
|
|
dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
|
|
} else
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
|
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
|
static int set_dac_range(struct task_struct *child,
|
|
struct ppc_hw_breakpoint *bp_info)
|
|
{
|
|
int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
|
|
|
|
/* We don't allow range watchpoints to be used with DVC */
|
|
if (bp_info->condition_mode)
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Best effort to verify the address range. The user/supervisor bits
|
|
* prevent trapping in kernel space, but let's fail on an obvious bad
|
|
* range. The simple test on the mask is not fool-proof, and any
|
|
* exclusive range will spill over into kernel space.
|
|
*/
|
|
if (bp_info->addr >= TASK_SIZE)
|
|
return -EIO;
|
|
if (mode == PPC_BREAKPOINT_MODE_MASK) {
|
|
/*
|
|
* dac2 is a bitmask. Don't allow a mask that makes a
|
|
* kernel space address from a valid dac1 value
|
|
*/
|
|
if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
|
|
return -EIO;
|
|
} else {
|
|
/*
|
|
* For range breakpoints, addr2 must also be a valid address
|
|
*/
|
|
if (bp_info->addr2 >= TASK_SIZE)
|
|
return -EIO;
|
|
}
|
|
|
|
if (child->thread.dbcr0 &
|
|
(DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
|
|
return -ENOSPC;
|
|
|
|
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
|
|
child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
|
|
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
|
child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
|
|
child->thread.dac1 = bp_info->addr;
|
|
child->thread.dac2 = bp_info->addr2;
|
|
if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
|
|
child->thread.dbcr2 |= DBCR2_DAC12M;
|
|
else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
|
|
child->thread.dbcr2 |= DBCR2_DAC12MX;
|
|
else /* PPC_BREAKPOINT_MODE_MASK */
|
|
child->thread.dbcr2 |= DBCR2_DAC12MM;
|
|
child->thread.regs->msr |= MSR_DE;
|
|
|
|
return 5;
|
|
}
|
|
#endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
|
|
|
|
static long ppc_set_hwdebug(struct task_struct *child,
|
|
struct ppc_hw_breakpoint *bp_info)
|
|
{
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
|
int len = 0;
|
|
struct thread_struct *thread = &(child->thread);
|
|
struct perf_event *bp;
|
|
struct perf_event_attr attr;
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
|
#ifndef CONFIG_PPC_ADV_DEBUG_REGS
|
|
unsigned long dabr;
|
|
#endif
|
|
|
|
if (bp_info->version != 1)
|
|
return -ENOTSUPP;
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
/*
|
|
* Check for invalid flags and combinations
|
|
*/
|
|
if ((bp_info->trigger_type == 0) ||
|
|
(bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
|
|
PPC_BREAKPOINT_TRIGGER_RW)) ||
|
|
(bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
|
|
(bp_info->condition_mode &
|
|
~(PPC_BREAKPOINT_CONDITION_MODE |
|
|
PPC_BREAKPOINT_CONDITION_BE_ALL)))
|
|
return -EINVAL;
|
|
#if CONFIG_PPC_ADV_DEBUG_DVCS == 0
|
|
if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
|
|
return -EINVAL;
|
|
#endif
|
|
|
|
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
|
|
if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
|
|
(bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
|
|
return -EINVAL;
|
|
return set_instruction_bp(child, bp_info);
|
|
}
|
|
if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
|
|
return set_dac(child, bp_info);
|
|
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
|
return set_dac_range(child, bp_info);
|
|
#else
|
|
return -EINVAL;
|
|
#endif
|
|
#else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
|
|
/*
|
|
* We only support one data breakpoint
|
|
*/
|
|
if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
|
|
(bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
|
|
bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
|
|
return -EINVAL;
|
|
|
|
if ((unsigned long)bp_info->addr >= TASK_SIZE)
|
|
return -EIO;
|
|
|
|
dabr = (unsigned long)bp_info->addr & ~7UL;
|
|
dabr |= DABR_TRANSLATION;
|
|
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
|
|
dabr |= DABR_DATA_READ;
|
|
if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
|
|
dabr |= DABR_DATA_WRITE;
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
|
if (ptrace_get_breakpoints(child) < 0)
|
|
return -ESRCH;
|
|
|
|
/*
|
|
* Check if the request is for 'range' breakpoints. We can
|
|
* support it if range < 8 bytes.
|
|
*/
|
|
if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) {
|
|
len = bp_info->addr2 - bp_info->addr;
|
|
} else if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
|
|
ptrace_put_breakpoints(child);
|
|
return -EINVAL;
|
|
}
|
|
bp = thread->ptrace_bps[0];
|
|
if (bp) {
|
|
ptrace_put_breakpoints(child);
|
|
return -ENOSPC;
|
|
}
|
|
|
|
/* Create a new breakpoint request if one doesn't exist already */
|
|
hw_breakpoint_init(&attr);
|
|
attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
|
|
attr.bp_len = len;
|
|
arch_bp_generic_fields(dabr & (DABR_DATA_WRITE | DABR_DATA_READ),
|
|
&attr.bp_type);
|
|
|
|
thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
|
|
ptrace_triggered, NULL, child);
|
|
if (IS_ERR(bp)) {
|
|
thread->ptrace_bps[0] = NULL;
|
|
ptrace_put_breakpoints(child);
|
|
return PTR_ERR(bp);
|
|
}
|
|
|
|
ptrace_put_breakpoints(child);
|
|
return 1;
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
|
|
|
if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
|
|
return -EINVAL;
|
|
|
|
if (child->thread.dabr)
|
|
return -ENOSPC;
|
|
|
|
child->thread.dabr = dabr;
|
|
child->thread.dabrx = DABRX_ALL;
|
|
|
|
return 1;
|
|
#endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
|
|
}
|
|
|
|
static long ppc_del_hwdebug(struct task_struct *child, long data)
|
|
{
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
|
int ret = 0;
|
|
struct thread_struct *thread = &(child->thread);
|
|
struct perf_event *bp;
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
int rc;
|
|
|
|
if (data <= 4)
|
|
rc = del_instruction_bp(child, (int)data);
|
|
else
|
|
rc = del_dac(child, (int)data - 4);
|
|
|
|
if (!rc) {
|
|
if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
|
|
child->thread.dbcr1)) {
|
|
child->thread.dbcr0 &= ~DBCR0_IDM;
|
|
child->thread.regs->msr &= ~MSR_DE;
|
|
}
|
|
}
|
|
return rc;
|
|
#else
|
|
if (data != 1)
|
|
return -EINVAL;
|
|
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
|
if (ptrace_get_breakpoints(child) < 0)
|
|
return -ESRCH;
|
|
|
|
bp = thread->ptrace_bps[0];
|
|
if (bp) {
|
|
unregister_hw_breakpoint(bp);
|
|
thread->ptrace_bps[0] = NULL;
|
|
} else
|
|
ret = -ENOENT;
|
|
ptrace_put_breakpoints(child);
|
|
return ret;
|
|
#else /* CONFIG_HAVE_HW_BREAKPOINT */
|
|
if (child->thread.dabr == 0)
|
|
return -ENOENT;
|
|
|
|
child->thread.dabr = 0;
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
|
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
long arch_ptrace(struct task_struct *child, long request,
|
|
unsigned long addr, unsigned long data)
|
|
{
|
|
int ret = -EPERM;
|
|
void __user *datavp = (void __user *) data;
|
|
unsigned long __user *datalp = datavp;
|
|
|
|
switch (request) {
|
|
/* read the word at location addr in the USER area. */
|
|
case PTRACE_PEEKUSR: {
|
|
unsigned long index, tmp;
|
|
|
|
ret = -EIO;
|
|
/* convert to index and check */
|
|
#ifdef CONFIG_PPC32
|
|
index = addr >> 2;
|
|
if ((addr & 3) || (index > PT_FPSCR)
|
|
|| (child->thread.regs == NULL))
|
|
#else
|
|
index = addr >> 3;
|
|
if ((addr & 7) || (index > PT_FPSCR))
|
|
#endif
|
|
break;
|
|
|
|
CHECK_FULL_REGS(child->thread.regs);
|
|
if (index < PT_FPR0) {
|
|
tmp = ptrace_get_reg(child, (int) index);
|
|
} else {
|
|
unsigned int fpidx = index - PT_FPR0;
|
|
|
|
flush_fp_to_thread(child);
|
|
if (fpidx < (PT_FPSCR - PT_FPR0))
|
|
tmp = ((unsigned long *)child->thread.fpr)
|
|
[fpidx * TS_FPRWIDTH];
|
|
else
|
|
tmp = child->thread.fpscr.val;
|
|
}
|
|
ret = put_user(tmp, datalp);
|
|
break;
|
|
}
|
|
|
|
/* write the word at location addr in the USER area */
|
|
case PTRACE_POKEUSR: {
|
|
unsigned long index;
|
|
|
|
ret = -EIO;
|
|
/* convert to index and check */
|
|
#ifdef CONFIG_PPC32
|
|
index = addr >> 2;
|
|
if ((addr & 3) || (index > PT_FPSCR)
|
|
|| (child->thread.regs == NULL))
|
|
#else
|
|
index = addr >> 3;
|
|
if ((addr & 7) || (index > PT_FPSCR))
|
|
#endif
|
|
break;
|
|
|
|
CHECK_FULL_REGS(child->thread.regs);
|
|
if (index < PT_FPR0) {
|
|
ret = ptrace_put_reg(child, index, data);
|
|
} else {
|
|
unsigned int fpidx = index - PT_FPR0;
|
|
|
|
flush_fp_to_thread(child);
|
|
if (fpidx < (PT_FPSCR - PT_FPR0))
|
|
((unsigned long *)child->thread.fpr)
|
|
[fpidx * TS_FPRWIDTH] = data;
|
|
else
|
|
child->thread.fpscr.val = data;
|
|
ret = 0;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case PPC_PTRACE_GETHWDBGINFO: {
|
|
struct ppc_debug_info dbginfo;
|
|
|
|
dbginfo.version = 1;
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
|
|
dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
|
|
dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
|
|
dbginfo.data_bp_alignment = 4;
|
|
dbginfo.sizeof_condition = 4;
|
|
dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
|
|
PPC_DEBUG_FEATURE_INSN_BP_MASK;
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
|
|
dbginfo.features |=
|
|
PPC_DEBUG_FEATURE_DATA_BP_RANGE |
|
|
PPC_DEBUG_FEATURE_DATA_BP_MASK;
|
|
#endif
|
|
#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
|
|
dbginfo.num_instruction_bps = 0;
|
|
dbginfo.num_data_bps = 1;
|
|
dbginfo.num_condition_regs = 0;
|
|
#ifdef CONFIG_PPC64
|
|
dbginfo.data_bp_alignment = 8;
|
|
#else
|
|
dbginfo.data_bp_alignment = 4;
|
|
#endif
|
|
dbginfo.sizeof_condition = 0;
|
|
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
|
dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
|
|
#else
|
|
dbginfo.features = 0;
|
|
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
|
#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
|
|
|
|
if (!access_ok(VERIFY_WRITE, datavp,
|
|
sizeof(struct ppc_debug_info)))
|
|
return -EFAULT;
|
|
ret = __copy_to_user(datavp, &dbginfo,
|
|
sizeof(struct ppc_debug_info)) ?
|
|
-EFAULT : 0;
|
|
break;
|
|
}
|
|
|
|
case PPC_PTRACE_SETHWDEBUG: {
|
|
struct ppc_hw_breakpoint bp_info;
|
|
|
|
if (!access_ok(VERIFY_READ, datavp,
|
|
sizeof(struct ppc_hw_breakpoint)))
|
|
return -EFAULT;
|
|
ret = __copy_from_user(&bp_info, datavp,
|
|
sizeof(struct ppc_hw_breakpoint)) ?
|
|
-EFAULT : 0;
|
|
if (!ret)
|
|
ret = ppc_set_hwdebug(child, &bp_info);
|
|
break;
|
|
}
|
|
|
|
case PPC_PTRACE_DELHWDEBUG: {
|
|
ret = ppc_del_hwdebug(child, data);
|
|
break;
|
|
}
|
|
|
|
case PTRACE_GET_DEBUGREG: {
|
|
ret = -EINVAL;
|
|
/* We only support one DABR and no IABRS at the moment */
|
|
if (addr > 0)
|
|
break;
|
|
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
|
ret = put_user(child->thread.dac1, datalp);
|
|
#else
|
|
ret = put_user(child->thread.dabr, datalp);
|
|
#endif
|
|
break;
|
|
}
|
|
|
|
case PTRACE_SET_DEBUGREG:
|
|
ret = ptrace_set_debugreg(child, addr, data);
|
|
break;
|
|
|
|
#ifdef CONFIG_PPC64
|
|
case PTRACE_GETREGS64:
|
|
#endif
|
|
case PTRACE_GETREGS: /* Get all pt_regs from the child. */
|
|
return copy_regset_to_user(child, &user_ppc_native_view,
|
|
REGSET_GPR,
|
|
0, sizeof(struct pt_regs),
|
|
datavp);
|
|
|
|
#ifdef CONFIG_PPC64
|
|
case PTRACE_SETREGS64:
|
|
#endif
|
|
case PTRACE_SETREGS: /* Set all gp regs in the child. */
|
|
return copy_regset_from_user(child, &user_ppc_native_view,
|
|
REGSET_GPR,
|
|
0, sizeof(struct pt_regs),
|
|
datavp);
|
|
|
|
case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
|
|
return copy_regset_to_user(child, &user_ppc_native_view,
|
|
REGSET_FPR,
|
|
0, sizeof(elf_fpregset_t),
|
|
datavp);
|
|
|
|
case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
|
|
return copy_regset_from_user(child, &user_ppc_native_view,
|
|
REGSET_FPR,
|
|
0, sizeof(elf_fpregset_t),
|
|
datavp);
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
case PTRACE_GETVRREGS:
|
|
return copy_regset_to_user(child, &user_ppc_native_view,
|
|
REGSET_VMX,
|
|
0, (33 * sizeof(vector128) +
|
|
sizeof(u32)),
|
|
datavp);
|
|
|
|
case PTRACE_SETVRREGS:
|
|
return copy_regset_from_user(child, &user_ppc_native_view,
|
|
REGSET_VMX,
|
|
0, (33 * sizeof(vector128) +
|
|
sizeof(u32)),
|
|
datavp);
|
|
#endif
|
|
#ifdef CONFIG_VSX
|
|
case PTRACE_GETVSRREGS:
|
|
return copy_regset_to_user(child, &user_ppc_native_view,
|
|
REGSET_VSX,
|
|
0, 32 * sizeof(double),
|
|
datavp);
|
|
|
|
case PTRACE_SETVSRREGS:
|
|
return copy_regset_from_user(child, &user_ppc_native_view,
|
|
REGSET_VSX,
|
|
0, 32 * sizeof(double),
|
|
datavp);
|
|
#endif
|
|
#ifdef CONFIG_SPE
|
|
case PTRACE_GETEVRREGS:
|
|
/* Get the child spe register state. */
|
|
return copy_regset_to_user(child, &user_ppc_native_view,
|
|
REGSET_SPE, 0, 35 * sizeof(u32),
|
|
datavp);
|
|
|
|
case PTRACE_SETEVRREGS:
|
|
/* Set the child spe register state. */
|
|
return copy_regset_from_user(child, &user_ppc_native_view,
|
|
REGSET_SPE, 0, 35 * sizeof(u32),
|
|
datavp);
|
|
#endif
|
|
|
|
default:
|
|
ret = ptrace_request(child, request, addr, data);
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* We must return the syscall number to actually look up in the table.
|
|
* This can be -1L to skip running any syscall at all.
|
|
*/
|
|
long do_syscall_trace_enter(struct pt_regs *regs)
|
|
{
|
|
long ret = 0;
|
|
|
|
secure_computing_strict(regs->gpr[0]);
|
|
|
|
if (test_thread_flag(TIF_SYSCALL_TRACE) &&
|
|
tracehook_report_syscall_entry(regs))
|
|
/*
|
|
* Tracing decided this syscall should not happen.
|
|
* We'll return a bogus call number to get an ENOSYS
|
|
* error, but leave the original number in regs->gpr[0].
|
|
*/
|
|
ret = -1L;
|
|
|
|
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
|
|
trace_sys_enter(regs, regs->gpr[0]);
|
|
|
|
#ifdef CONFIG_PPC64
|
|
if (!is_32bit_task())
|
|
audit_syscall_entry(AUDIT_ARCH_PPC64,
|
|
regs->gpr[0],
|
|
regs->gpr[3], regs->gpr[4],
|
|
regs->gpr[5], regs->gpr[6]);
|
|
else
|
|
#endif
|
|
audit_syscall_entry(AUDIT_ARCH_PPC,
|
|
regs->gpr[0],
|
|
regs->gpr[3] & 0xffffffff,
|
|
regs->gpr[4] & 0xffffffff,
|
|
regs->gpr[5] & 0xffffffff,
|
|
regs->gpr[6] & 0xffffffff);
|
|
|
|
return ret ?: regs->gpr[0];
|
|
}
|
|
|
|
void do_syscall_trace_leave(struct pt_regs *regs)
|
|
{
|
|
int step;
|
|
|
|
audit_syscall_exit(regs);
|
|
|
|
if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
|
|
trace_sys_exit(regs, regs->result);
|
|
|
|
step = test_thread_flag(TIF_SINGLESTEP);
|
|
if (step || test_thread_flag(TIF_SYSCALL_TRACE))
|
|
tracehook_report_syscall_exit(regs, step);
|
|
}
|