529 lines
15 KiB
C
529 lines
15 KiB
C
/*
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* OMAP4 CM instance functions
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*
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* Copyright (C) 2009 Nokia Corporation
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* Copyright (C) 2008-2011 Texas Instruments, Inc.
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* Paul Walmsley
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* Rajendra Nayak <rnayak@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is needed since CM instances can be in the PRM, PRCM_MPU, CM1,
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* or CM2 hardware modules. For example, the EMU_CM CM instance is in
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* the PRM hardware module. What a mess...
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "cm.h"
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#include "cm1_44xx.h"
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#include "cm2_44xx.h"
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#include "cm44xx.h"
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#include "cm-regbits-34xx.h"
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#include "prcm44xx.h"
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#include "prm44xx.h"
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#include "prcm_mpu44xx.h"
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#include "prcm-common.h"
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#define OMAP4430_IDLEST_SHIFT 16
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#define OMAP4430_IDLEST_MASK (0x3 << 16)
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#define OMAP4430_CLKTRCTRL_SHIFT 0
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#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
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#define OMAP4430_MODULEMODE_SHIFT 0
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#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
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/*
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* CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
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*
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* 0x0 func: Module is fully functional, including OCP
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* 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
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* abortion
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* 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
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* using separate functional clock
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* 0x3 disabled: Module is disabled and cannot be accessed
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*
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*/
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#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
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#define CLKCTRL_IDLEST_INTRANSITION 0x1
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#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
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#define CLKCTRL_IDLEST_DISABLED 0x3
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static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
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/**
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* omap_cm_base_init - Populates the cm partitions
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*
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* Populates the base addresses of the _cm_bases
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* array used for read/write of cm module registers.
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*/
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static void omap_cm_base_init(void)
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{
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_cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
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_cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
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_cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
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_cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
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}
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/* Private functions */
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static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx);
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/**
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* _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
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* @part: PRCM partition ID that the CM_CLKCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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*
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* Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
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* bit 0.
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*/
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static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs)
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{
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u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
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v &= OMAP4430_IDLEST_MASK;
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v >>= OMAP4430_IDLEST_SHIFT;
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return v;
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}
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/**
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* _is_module_ready - can module registers be accessed without causing an abort?
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* @part: PRCM partition ID that the CM_CLKCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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*
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* Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
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* *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
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*/
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static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs)
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{
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u32 v;
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v = _clkctrl_idlest(part, inst, clkctrl_offs);
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return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
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v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
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}
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/* Read a register in a CM instance */
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static u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_cm_bases[part]);
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return readl_relaxed(_cm_bases[part] + inst + idx);
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}
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/* Write into a register in a CM instance */
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static void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
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{
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BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
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part == OMAP4430_INVALID_PRCM_PARTITION ||
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!_cm_bases[part]);
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writel_relaxed(val, _cm_bases[part] + inst + idx);
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}
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/* Read-modify-write a register in CM1. Caller must lock */
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static u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, u16 inst,
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s16 idx)
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{
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u32 v;
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v = omap4_cminst_read_inst_reg(part, inst, idx);
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v &= ~mask;
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v |= bits;
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omap4_cminst_write_inst_reg(v, part, inst, idx);
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return v;
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}
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static u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
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{
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return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
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}
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static u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst,
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s16 idx)
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{
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return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
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}
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static u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
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{
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u32 v;
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v = omap4_cminst_read_inst_reg(part, inst, idx);
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v &= mask;
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v >>= __ffs(mask);
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return v;
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}
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/*
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*
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*/
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/**
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* _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
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* @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
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* @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* @c must be the unshifted value for CLKTRCTRL - i.e., this function
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* will handle the shift itself.
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*/
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static void _clktrctrl_write(u8 c, u8 part, u16 inst, u16 cdoffs)
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{
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u32 v;
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v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
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v &= ~OMAP4430_CLKTRCTRL_MASK;
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v |= c << OMAP4430_CLKTRCTRL_SHIFT;
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omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
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}
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/**
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* omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
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* @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
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* is in hardware-supervised idle mode, or 0 otherwise.
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*/
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static bool omap4_cminst_is_clkdm_in_hwsup(u8 part, u16 inst, u16 cdoffs)
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{
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u32 v;
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v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
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v &= OMAP4430_CLKTRCTRL_MASK;
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v >>= OMAP4430_CLKTRCTRL_SHIFT;
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return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
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}
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/**
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* omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
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* @part: PRCM partition ID that the clockdomain registers exist in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Put a clockdomain referred to by (@part, @inst, @cdoffs) into
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* hardware-supervised idle mode. No return value.
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*/
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static void omap4_cminst_clkdm_enable_hwsup(u8 part, u16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
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}
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/**
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* omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
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* @part: PRCM partition ID that the clockdomain registers exist in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Put a clockdomain referred to by (@part, @inst, @cdoffs) into
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* software-supervised idle mode, i.e., controlled manually by the
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* Linux OMAP clockdomain code. No return value.
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*/
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static void omap4_cminst_clkdm_disable_hwsup(u8 part, u16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
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}
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/**
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* omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
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* @part: PRCM partition ID that the clockdomain registers exist in
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* @inst: CM instance register offset (*_INST macro)
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* @cdoffs: Clockdomain register offset (*_CDOFFS macro)
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*
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* Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
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* waking it up. No return value.
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*/
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static void omap4_cminst_clkdm_force_wakeup(u8 part, u16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
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}
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/*
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*
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*/
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static void omap4_cminst_clkdm_force_sleep(u8 part, u16 inst, u16 cdoffs)
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{
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_clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
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}
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/**
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* omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
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* @part: PRCM partition ID that the CM_CLKCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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* @bit_shift: bit shift for the register, ignored for OMAP4+
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*
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* Wait for the module IDLEST to be functional. If the idle state is in any
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* the non functional state (trans, idle or disabled), module and thus the
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* sysconfig cannot be accessed and will probably lead to an "imprecise
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* external abort"
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*/
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static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
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u8 bit_shift)
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{
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int i = 0;
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if (!clkctrl_offs)
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return 0;
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omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs),
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MAX_MODULE_READY_TIME, i);
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return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
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}
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/**
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* omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
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* state
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* @part: PRCM partition ID that the CM_CLKCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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* @bit_shift: Bit shift for the register, ignored for OMAP4+
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*
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* Wait for the module IDLEST to be disabled. Some PRCM transition,
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* like reset assertion or parent clock de-activation must wait the
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* module to be fully disabled.
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*/
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static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
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u8 bit_shift)
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{
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int i = 0;
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if (!clkctrl_offs)
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return 0;
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omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) ==
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CLKCTRL_IDLEST_DISABLED),
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MAX_MODULE_DISABLE_TIME, i);
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return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY;
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}
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/**
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* omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
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* @mode: Module mode (SW or HW)
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* @part: PRCM partition ID that the CM_CLKCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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*
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* No return value.
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*/
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static void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
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u16 clkctrl_offs)
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{
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u32 v;
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v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
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v &= ~OMAP4430_MODULEMODE_MASK;
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v |= mode << OMAP4430_MODULEMODE_SHIFT;
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omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
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}
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/**
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* omap4_cminst_module_disable - Disable the module inside CLKCTRL
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* @part: PRCM partition ID that the CM_CLKCTRL register exists in
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* @inst: CM instance register offset (*_INST macro)
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* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
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*
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* No return value.
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*/
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static void omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
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{
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u32 v;
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v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
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v &= ~OMAP4430_MODULEMODE_MASK;
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omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
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}
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/*
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* Clockdomain low-level functions
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*/
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static int omap4_clkdm_add_wkup_sleep_dep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->prcm_partition,
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clkdm1->cm_inst, clkdm1->clkdm_offs +
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OMAP4_CM_STATICDEP);
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return 0;
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}
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static int omap4_clkdm_del_wkup_sleep_dep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->prcm_partition,
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clkdm1->cm_inst, clkdm1->clkdm_offs +
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OMAP4_CM_STATICDEP);
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return 0;
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}
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static int omap4_clkdm_read_wkup_sleep_dep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,
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clkdm1->cm_inst,
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clkdm1->clkdm_offs +
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OMAP4_CM_STATICDEP,
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(1 << clkdm2->dep_bit));
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}
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static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
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{
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struct clkdm_dep *cd;
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u32 mask = 0;
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if (!clkdm->prcm_partition)
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return 0;
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for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
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if (!cd->clkdm)
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continue; /* only happens if data is erroneous */
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mask |= 1 << cd->clkdm->dep_bit;
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cd->wkdep_usecount = 0;
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}
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omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
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clkdm->cm_inst, clkdm->clkdm_offs +
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OMAP4_CM_STATICDEP);
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return 0;
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}
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static int omap4_clkdm_sleep(struct clockdomain *clkdm)
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{
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if (clkdm->flags & CLKDM_CAN_HWSUP)
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omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
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clkdm->cm_inst,
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clkdm->clkdm_offs);
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else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
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omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
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clkdm->cm_inst,
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clkdm->clkdm_offs);
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else
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return -EINVAL;
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return 0;
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}
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static int omap4_clkdm_wakeup(struct clockdomain *clkdm)
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{
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omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
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clkdm->cm_inst, clkdm->clkdm_offs);
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return 0;
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}
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static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
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{
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omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
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clkdm->cm_inst, clkdm->clkdm_offs);
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}
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static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
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{
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if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
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omap4_clkdm_wakeup(clkdm);
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else
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omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
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clkdm->cm_inst,
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clkdm->clkdm_offs);
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}
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static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
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{
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if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
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return omap4_clkdm_wakeup(clkdm);
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return 0;
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}
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static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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if (!clkdm->prcm_partition)
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return 0;
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|
|
/*
|
|
* The CLKDM_MISSING_IDLE_REPORTING flag documentation has
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|
* more details on the unpleasant problem this is working
|
|
* around
|
|
*/
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if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
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|
!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
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omap4_clkdm_allow_idle(clkdm);
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return 0;
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|
}
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|
|
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hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
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|
clkdm->cm_inst, clkdm->clkdm_offs);
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|
|
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if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
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|
omap4_clkdm_sleep(clkdm);
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|
|
|
return 0;
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|
}
|
|
|
|
struct clkdm_ops omap4_clkdm_operations = {
|
|
.clkdm_add_wkdep = omap4_clkdm_add_wkup_sleep_dep,
|
|
.clkdm_del_wkdep = omap4_clkdm_del_wkup_sleep_dep,
|
|
.clkdm_read_wkdep = omap4_clkdm_read_wkup_sleep_dep,
|
|
.clkdm_clear_all_wkdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
|
|
.clkdm_add_sleepdep = omap4_clkdm_add_wkup_sleep_dep,
|
|
.clkdm_del_sleepdep = omap4_clkdm_del_wkup_sleep_dep,
|
|
.clkdm_read_sleepdep = omap4_clkdm_read_wkup_sleep_dep,
|
|
.clkdm_clear_all_sleepdeps = omap4_clkdm_clear_all_wkup_sleep_deps,
|
|
.clkdm_sleep = omap4_clkdm_sleep,
|
|
.clkdm_wakeup = omap4_clkdm_wakeup,
|
|
.clkdm_allow_idle = omap4_clkdm_allow_idle,
|
|
.clkdm_deny_idle = omap4_clkdm_deny_idle,
|
|
.clkdm_clk_enable = omap4_clkdm_clk_enable,
|
|
.clkdm_clk_disable = omap4_clkdm_clk_disable,
|
|
};
|
|
|
|
struct clkdm_ops am43xx_clkdm_operations = {
|
|
.clkdm_sleep = omap4_clkdm_sleep,
|
|
.clkdm_wakeup = omap4_clkdm_wakeup,
|
|
.clkdm_allow_idle = omap4_clkdm_allow_idle,
|
|
.clkdm_deny_idle = omap4_clkdm_deny_idle,
|
|
.clkdm_clk_enable = omap4_clkdm_clk_enable,
|
|
.clkdm_clk_disable = omap4_clkdm_clk_disable,
|
|
};
|
|
|
|
static struct cm_ll_data omap4xxx_cm_ll_data = {
|
|
.wait_module_ready = &omap4_cminst_wait_module_ready,
|
|
.wait_module_idle = &omap4_cminst_wait_module_idle,
|
|
.module_enable = &omap4_cminst_module_enable,
|
|
.module_disable = &omap4_cminst_module_disable,
|
|
};
|
|
|
|
int __init omap4_cm_init(const struct omap_prcm_init_data *data)
|
|
{
|
|
omap_cm_base_init();
|
|
|
|
return cm_register(&omap4xxx_cm_ll_data);
|
|
}
|
|
|
|
static void __exit omap4_cm_exit(void)
|
|
{
|
|
cm_unregister(&omap4xxx_cm_ll_data);
|
|
}
|
|
__exitcall(omap4_cm_exit);
|