168 lines
6.0 KiB
C
168 lines
6.0 KiB
C
/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <drm/drmP.h>
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#include "meson_drv.h"
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#include "meson_vclk.h"
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/*
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* VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
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* We handle the following encodings :
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* - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
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*
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* What is missing :
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* - HDMI Pixel Clocks generation
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*/
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/* HHI Registers */
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#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
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#define VID_PLL_EN BIT(19)
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#define VID_PLL_BYPASS BIT(18)
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#define VID_PLL_PRESET BIT(15)
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#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
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#define VCLK2_DIV_MASK 0xff
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#define VCLK2_DIV_EN BIT(16)
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#define VCLK2_DIV_RESET BIT(17)
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#define CTS_VDAC_SEL_MASK (0xf << 28)
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#define CTS_VDAC_SEL_SHIFT 28
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#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
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#define VCLK2_EN BIT(19)
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#define VCLK2_SEL_MASK (0x7 << 16)
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#define VCLK2_SEL_SHIFT 16
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#define VCLK2_SOFT_RESET BIT(15)
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#define VCLK2_DIV1_EN BIT(0)
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#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
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#define CTS_ENCI_SEL_MASK (0xf << 28)
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#define CTS_ENCI_SEL_SHIFT 28
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#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
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#define CTS_ENCI_EN BIT(0)
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#define CTS_VDAC_EN BIT(4)
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#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
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#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
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#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
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#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
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#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
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#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
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#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
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#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
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#define HDMI_PLL_RESET BIT(28)
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#define HDMI_PLL_LOCK BIT(31)
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/*
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* Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
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*
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* TOFIX: Refactor into table to also handle HDMI frequency and paths
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*/
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static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
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{
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unsigned int val;
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/* Setup PLL to output 1.485GHz */
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if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) {
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
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} else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
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meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) {
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
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regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
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/* Reset PLL */
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regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
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HDMI_PLL_RESET, HDMI_PLL_RESET);
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regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
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HDMI_PLL_RESET, 0);
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}
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/* Poll for lock bit */
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regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
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(val & HDMI_PLL_LOCK), 10, 0);
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/* Disable VCLK2 */
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regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
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/* Disable vid_pll output clock */
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regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
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regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
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/* Enable vid_pll bypass to HDMI pll */
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regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
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VID_PLL_BYPASS, VID_PLL_BYPASS);
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/* Enable the vid_pll output clock */
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regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
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VID_PLL_EN, VID_PLL_EN);
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/* Setup the VCLK2 divider value to achieve 27MHz */
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regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
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VCLK2_DIV_MASK, (55 - 1));
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/* select vid_pll for vclk2 */
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regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
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VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
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/* enable vclk2 gate */
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regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
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/* select vclk_div1 for enci */
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regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
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CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
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/* select vclk_div1 for vdac */
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regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
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CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
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/* release vclk2_div_reset and enable vclk2_div */
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regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
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VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
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/* enable vclk2_div1 gate */
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regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
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VCLK2_DIV1_EN, VCLK2_DIV1_EN);
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/* reset vclk2 */
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regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
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VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
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regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
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VCLK2_SOFT_RESET, 0);
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/* enable enci_clk */
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regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
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CTS_ENCI_EN, CTS_ENCI_EN);
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/* enable vdac_clk */
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regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
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CTS_VDAC_EN, CTS_VDAC_EN);
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}
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void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
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unsigned int freq)
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{
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if (target == MESON_VCLK_TARGET_CVBS && freq == MESON_VCLK_CVBS)
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meson_venci_cvbs_clock_config(priv);
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}
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