147 lines
3.5 KiB
C
147 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017, Intel Corporation
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*/
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include "stratix10-clk.h"
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#include "clk.h"
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/* Clock Manager offsets */
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#define CLK_MGR_PLL_CLK_SRC_SHIFT 16
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#define CLK_MGR_PLL_CLK_SRC_MASK 0x3
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/* PLL Clock enable bits */
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#define SOCFPGA_PLL_POWER 0
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#define SOCFPGA_PLL_RESET_MASK 0x2
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#define SOCFPGA_PLL_REFDIV_MASK 0x00003F00
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#define SOCFPGA_PLL_REFDIV_SHIFT 8
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#define SOCFPGA_PLL_MDIV_MASK 0xFF000000
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#define SOCFPGA_PLL_MDIV_SHIFT 24
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#define SWCTRLBTCLKSEL_MASK 0x200
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#define SWCTRLBTCLKSEL_SHIFT 9
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#define SOCFPGA_BOOT_CLK "boot_clk"
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#define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw)
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
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unsigned long mdiv;
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unsigned long refdiv;
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unsigned long reg;
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unsigned long long vco_freq;
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/* read VCO1 reg for numerator and denominator */
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reg = readl(socfpgaclk->hw.reg);
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refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT;
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vco_freq = (unsigned long long)parent_rate / refdiv;
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/* Read mdiv and fdiv from the fdbck register */
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reg = readl(socfpgaclk->hw.reg + 0x4);
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mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
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vco_freq = (unsigned long long)vco_freq * (mdiv + 6);
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return (unsigned long)vco_freq;
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}
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static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
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u32 div = 1;
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div = ((readl(socfpgaclk->hw.reg) &
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SWCTRLBTCLKSEL_MASK) >>
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SWCTRLBTCLKSEL_SHIFT);
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div += 1;
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return parent_rate /= div;
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}
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static u8 clk_pll_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
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u32 pll_src;
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pll_src = readl(socfpgaclk->hw.reg);
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return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) &
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CLK_MGR_PLL_CLK_SRC_MASK;
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}
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static u8 clk_boot_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
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u32 pll_src;
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pll_src = readl(socfpgaclk->hw.reg);
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return (pll_src >> SWCTRLBTCLKSEL_SHIFT) &
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SWCTRLBTCLKSEL_MASK;
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}
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static int clk_pll_prepare(struct clk_hw *hwclk)
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{
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struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
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u32 reg;
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/* Bring PLL out of reset */
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reg = readl(socfpgaclk->hw.reg);
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reg |= SOCFPGA_PLL_RESET_MASK;
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writel(reg, socfpgaclk->hw.reg);
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return 0;
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}
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static struct clk_ops clk_pll_ops = {
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.recalc_rate = clk_pll_recalc_rate,
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.get_parent = clk_pll_get_parent,
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.prepare = clk_pll_prepare,
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};
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static struct clk_ops clk_boot_ops = {
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.recalc_rate = clk_boot_clk_recalc_rate,
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.get_parent = clk_boot_get_parent,
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.prepare = clk_pll_prepare,
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};
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struct clk *s10_register_pll(const char *name, const char * const *parent_names,
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u8 num_parents, unsigned long flags,
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void __iomem *reg, unsigned long offset)
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{
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struct clk *clk;
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struct socfpga_pll *pll_clk;
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struct clk_init_data init;
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pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
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if (WARN_ON(!pll_clk))
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return NULL;
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pll_clk->hw.reg = reg + offset;
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if (streq(name, SOCFPGA_BOOT_CLK))
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init.ops = &clk_boot_ops;
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else
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init.ops = &clk_pll_ops;
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init.name = name;
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init.flags = flags;
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init.num_parents = num_parents;
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init.parent_names = parent_names;
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pll_clk->hw.hw.init = &init;
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pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
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clk_pll_ops.enable = clk_gate_ops.enable;
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clk_pll_ops.disable = clk_gate_ops.disable;
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clk = clk_register(NULL, &pll_clk->hw.hw);
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if (WARN_ON(IS_ERR(clk))) {
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kfree(pll_clk);
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return NULL;
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}
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return clk;
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}
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