145 lines
3.7 KiB
C
145 lines
3.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020, MIPI Alliance, Inc.
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*
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* Author: Nicolas Pitre <npitre@baylibre.com>
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*
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* Common HCI stuff
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*/
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#ifndef HCI_H
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#define HCI_H
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/* Handy logging macro to save on line length */
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#define DBG(x, ...) pr_devel("%s: " x "\n", __func__, ##__VA_ARGS__)
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/* 32-bit word aware bit and mask macros */
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#define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0)
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#define W1_MASK(h, l) GENMASK((h) - 32, (l) - 32)
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#define W2_MASK(h, l) GENMASK((h) - 64, (l) - 64)
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#define W3_MASK(h, l) GENMASK((h) - 96, (l) - 96)
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/* Same for single bit macros (trailing _ to align with W*_MASK width) */
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#define W0_BIT_(x) BIT((x) - 0)
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#define W1_BIT_(x) BIT((x) - 32)
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#define W2_BIT_(x) BIT((x) - 64)
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#define W3_BIT_(x) BIT((x) - 96)
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struct hci_cmd_ops;
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/* Our main structure */
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struct i3c_hci {
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struct i3c_master_controller master;
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void __iomem *base_regs;
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void __iomem *DAT_regs;
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void __iomem *DCT_regs;
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void __iomem *RHS_regs;
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void __iomem *PIO_regs;
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void __iomem *EXTCAPS_regs;
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void __iomem *AUTOCMD_regs;
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void __iomem *DEBUG_regs;
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const struct hci_io_ops *io;
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void *io_data;
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const struct hci_cmd_ops *cmd;
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atomic_t next_cmd_tid;
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u32 caps;
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unsigned int quirks;
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unsigned int DAT_entries;
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unsigned int DAT_entry_size;
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void *DAT_data;
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unsigned int DCT_entries;
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unsigned int DCT_entry_size;
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u8 version_major;
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u8 version_minor;
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u8 revision;
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u32 vendor_mipi_id;
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u32 vendor_version_id;
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u32 vendor_product_id;
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void *vendor_data;
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};
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/*
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* Structure to represent a master initiated transfer.
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* The rnw, data and data_len fields must be initialized before calling any
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* hci->cmd->*() method. The cmd method will initialize cmd_desc[] and
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* possibly modify (clear) the data field. Then xfer->cmd_desc[0] can
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* be augmented with CMD_0_ROC and/or CMD_0_TOC.
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* The completion field needs to be initialized before queueing with
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* hci->io->queue_xfer(), and requires CMD_0_ROC to be set.
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*/
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struct hci_xfer {
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u32 cmd_desc[4];
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u32 response;
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bool rnw;
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void *data;
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unsigned int data_len;
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unsigned int cmd_tid;
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struct completion *completion;
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union {
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struct {
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/* PIO specific */
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struct hci_xfer *next_xfer;
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struct hci_xfer *next_data;
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struct hci_xfer *next_resp;
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unsigned int data_left;
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u32 data_word_before_partial;
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};
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struct {
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/* DMA specific */
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dma_addr_t data_dma;
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int ring_number;
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int ring_entry;
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};
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};
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};
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static inline struct hci_xfer *hci_alloc_xfer(unsigned int n)
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{
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return kcalloc(n, sizeof(struct hci_xfer), GFP_KERNEL);
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}
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static inline void hci_free_xfer(struct hci_xfer *xfer, unsigned int n)
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{
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kfree(xfer);
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}
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/* This abstracts PIO vs DMA operations */
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struct hci_io_ops {
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bool (*irq_handler)(struct i3c_hci *hci, unsigned int mask);
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int (*queue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
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bool (*dequeue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
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int (*request_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
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const struct i3c_ibi_setup *req);
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void (*free_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev);
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void (*recycle_ibi_slot)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
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struct i3c_ibi_slot *slot);
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int (*init)(struct i3c_hci *hci);
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void (*cleanup)(struct i3c_hci *hci);
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};
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extern const struct hci_io_ops mipi_i3c_hci_pio;
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extern const struct hci_io_ops mipi_i3c_hci_dma;
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/* Our per device master private data */
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struct i3c_hci_dev_data {
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int dat_idx;
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void *ibi_data;
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};
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/* list of quirks */
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#define HCI_QUIRK_RAW_CCC BIT(1) /* CCC framing must be explicit */
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/* global functions */
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void mipi_i3c_hci_resume(struct i3c_hci *hci);
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void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
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void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
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#endif
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