618 lines
16 KiB
C
618 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* R-Car Gen3 Clock Pulse Generator
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*
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* Copyright (C) 2015-2018 Glider bvba
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*
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* Based on clk-rcar-gen3.c
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*
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* Copyright (C) 2015 Renesas Electronics Corp.
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*/
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#include <linux/bug.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/pm.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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#define CPG_PLL0CR 0x00d8
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#define CPG_PLL2CR 0x002c
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#define CPG_PLL4CR 0x01f4
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#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
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struct cpg_simple_notifier {
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struct notifier_block nb;
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void __iomem *reg;
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u32 saved;
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};
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static int cpg_simple_notifier_call(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct cpg_simple_notifier *csn =
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container_of(nb, struct cpg_simple_notifier, nb);
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switch (action) {
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case PM_EVENT_SUSPEND:
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csn->saved = readl(csn->reg);
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return NOTIFY_OK;
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case PM_EVENT_RESUME:
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writel(csn->saved, csn->reg);
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return NOTIFY_OK;
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}
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return NOTIFY_DONE;
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}
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static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
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struct cpg_simple_notifier *csn)
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{
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csn->nb.notifier_call = cpg_simple_notifier_call;
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raw_notifier_chain_register(notifiers, &csn->nb);
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}
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/*
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* Z Clock & Z2 Clock
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
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* parent - fixed parent. No clk_set_parent support
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*/
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#define CPG_FRQCRB 0x00000004
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#define CPG_FRQCRB_KICK BIT(31)
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#define CPG_FRQCRC 0x000000e0
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#define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8)
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#define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0)
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struct cpg_z_clk {
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struct clk_hw hw;
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void __iomem *reg;
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void __iomem *kick_reg;
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unsigned long mask;
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};
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#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
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static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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u32 val;
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val = readl(zclk->reg) & zclk->mask;
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mult = 32 - (val >> __ffs(zclk->mask));
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/* Factor of 2 is for fixed divider */
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return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2);
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}
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static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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/* Factor of 2 is for fixed divider */
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unsigned long prate = *parent_rate / 2;
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unsigned int mult;
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mult = div_u64(rate * 32ULL, prate);
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mult = clamp(mult, 1U, 32U);
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return (u64)prate * mult / 32;
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}
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static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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unsigned int i;
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u32 val, kick;
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/* Factor of 2 is for fixed divider */
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mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
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mult = clamp(mult, 1U, 32U);
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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return -EBUSY;
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val = readl(zclk->reg) & ~zclk->mask;
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val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
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writel(val, zclk->reg);
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/*
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* Set KICK bit in FRQCRB to update hardware setting and wait for
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* clock change completion.
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*/
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kick = readl(zclk->kick_reg);
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kick |= CPG_FRQCRB_KICK;
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writel(kick, zclk->kick_reg);
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/*
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* Note: There is no HW information about the worst case latency.
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*
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* Using experimental measurements, it seems that no more than
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* ~10 iterations are needed, independently of the CPU rate.
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* Since this value might be dependent of external xtal rate, pll1
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* rate or even the other emulation clocks rate, use 1000 as a
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* "super" safe value.
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*/
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for (i = 1000; i; i--) {
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if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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static const struct clk_ops cpg_z_clk_ops = {
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.recalc_rate = cpg_z_clk_recalc_rate,
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.round_rate = cpg_z_clk_round_rate,
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.set_rate = cpg_z_clk_set_rate,
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};
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static struct clk * __init cpg_z_clk_register(const char *name,
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const char *parent_name,
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void __iomem *reg,
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unsigned long mask)
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{
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struct clk_init_data init;
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struct cpg_z_clk *zclk;
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struct clk *clk;
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zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
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if (!zclk)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &cpg_z_clk_ops;
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init.flags = 0;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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zclk->reg = reg + CPG_FRQCRC;
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zclk->kick_reg = reg + CPG_FRQCRB;
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zclk->hw.init = &init;
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zclk->mask = mask;
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clk = clk_register(NULL, &zclk->hw);
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if (IS_ERR(clk))
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kfree(zclk);
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return clk;
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}
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/*
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* SDn Clock
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*/
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#define CPG_SD_STP_HCK BIT(9)
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#define CPG_SD_STP_CK BIT(8)
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#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
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#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
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#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
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{ \
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.val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
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((stp_ck) ? CPG_SD_STP_CK : 0) | \
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((sd_srcfc) << 2) | \
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((sd_fc) << 0), \
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.div = (sd_div), \
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}
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struct sd_div_table {
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u32 val;
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unsigned int div;
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};
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struct sd_clock {
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struct clk_hw hw;
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const struct sd_div_table *div_table;
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struct cpg_simple_notifier csn;
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unsigned int div_num;
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unsigned int div_min;
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unsigned int div_max;
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unsigned int cur_div_idx;
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};
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/* SDn divider
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* sd_srcfc sd_fc div
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* stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
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*-------------------------------------------------------------------
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* 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
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* 0 0 1 (2) 1 (4) 8 : SDR50
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* 1 0 2 (4) 1 (4) 16 : HS / SDR25
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* 1 0 3 (8) 1 (4) 32 : NS / SDR12
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* 1 0 4 (16) 1 (4) 64
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* 0 0 0 (1) 0 (2) 2
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* 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
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* 1 0 2 (4) 0 (2) 8
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* 1 0 3 (8) 0 (2) 16
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* 1 0 4 (16) 0 (2) 32
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*
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* NOTE: There is a quirk option to ignore the first row of the dividers
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* table when searching for suitable settings. This is because HS400 on
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* early ES versions of H3 and M3-W requires a specific setting to work.
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*/
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static const struct sd_div_table cpg_sd_div_table[] = {
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/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
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CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
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CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
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CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
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CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
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CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
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};
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#define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
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static int cpg_sd_clock_enable(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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u32 val = readl(clock->csn.reg);
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val &= ~(CPG_SD_STP_MASK);
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val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
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writel(val, clock->csn.reg);
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return 0;
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}
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static void cpg_sd_clock_disable(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg);
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}
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static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
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}
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static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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return DIV_ROUND_CLOSEST(parent_rate,
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clock->div_table[clock->cur_div_idx].div);
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}
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static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
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unsigned long rate,
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unsigned long parent_rate)
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{
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unsigned int div;
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if (!rate)
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rate = 1;
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
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}
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static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
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return DIV_ROUND_CLOSEST(*parent_rate, div);
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}
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static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sd_clock *clock = to_sd_clock(hw);
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unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
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u32 val;
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unsigned int i;
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for (i = 0; i < clock->div_num; i++)
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if (div == clock->div_table[i].div)
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break;
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if (i >= clock->div_num)
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return -EINVAL;
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clock->cur_div_idx = i;
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val = readl(clock->csn.reg);
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val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
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val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
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writel(val, clock->csn.reg);
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return 0;
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}
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static const struct clk_ops cpg_sd_clock_ops = {
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.enable = cpg_sd_clock_enable,
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.disable = cpg_sd_clock_disable,
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.is_enabled = cpg_sd_clock_is_enabled,
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.recalc_rate = cpg_sd_clock_recalc_rate,
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.round_rate = cpg_sd_clock_round_rate,
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.set_rate = cpg_sd_clock_set_rate,
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};
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static u32 cpg_quirks __initdata;
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#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
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#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
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#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
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static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
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void __iomem *base, const char *parent_name,
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struct raw_notifier_head *notifiers)
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{
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struct clk_init_data init;
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struct sd_clock *clock;
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struct clk *clk;
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unsigned int i;
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u32 val;
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clock = kzalloc(sizeof(*clock), GFP_KERNEL);
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if (!clock)
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return ERR_PTR(-ENOMEM);
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init.name = core->name;
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init.ops = &cpg_sd_clock_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clock->csn.reg = base + core->offset;
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clock->hw.init = &init;
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clock->div_table = cpg_sd_div_table;
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clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
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if (cpg_quirks & SD_SKIP_FIRST) {
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clock->div_table++;
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clock->div_num--;
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}
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val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
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val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
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writel(val, clock->csn.reg);
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clock->div_max = clock->div_table[0].div;
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clock->div_min = clock->div_max;
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for (i = 1; i < clock->div_num; i++) {
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clock->div_max = max(clock->div_max, clock->div_table[i].div);
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clock->div_min = min(clock->div_min, clock->div_table[i].div);
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}
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clk = clk_register(NULL, &clock->hw);
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if (IS_ERR(clk))
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goto free_clock;
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cpg_simple_notifier_register(notifiers, &clock->csn);
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return clk;
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free_clock:
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kfree(clock);
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return clk;
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}
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static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
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static unsigned int cpg_clk_extalr __initdata;
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static u32 cpg_mode __initdata;
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static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
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{
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.soc_id = "r8a7795", .revision = "ES1.0",
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.data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
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},
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{
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.soc_id = "r8a7795", .revision = "ES1.*",
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.data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
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},
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{
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.soc_id = "r8a7795", .revision = "ES2.0",
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.data = (void *)SD_SKIP_FIRST,
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},
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{
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.soc_id = "r8a7796", .revision = "ES1.0",
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.data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
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},
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{
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.soc_id = "r8a7796", .revision = "ES1.1",
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.data = (void *)SD_SKIP_FIRST,
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},
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{ /* sentinel */ }
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};
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struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers)
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{
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const struct clk *parent;
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unsigned int mult = 1;
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unsigned int div = 1;
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u32 value;
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parent = clks[core->parent & 0xffff]; /* some types use high bits */
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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switch (core->type) {
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case CLK_TYPE_GEN3_MAIN:
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div = cpg_pll_config->extal_div;
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break;
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case CLK_TYPE_GEN3_PLL0:
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/*
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* PLL0 is a configurable multiplier clock. Register it as a
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* fixed factor clock for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
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* the multiplier value.
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*/
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value = readl(base + CPG_PLL0CR);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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if (cpg_quirks & PLL_ERRATA)
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mult *= 2;
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break;
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case CLK_TYPE_GEN3_PLL1:
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mult = cpg_pll_config->pll1_mult;
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div = cpg_pll_config->pll1_div;
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break;
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case CLK_TYPE_GEN3_PLL2:
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/*
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* PLL2 is a configurable multiplier clock. Register it as a
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* fixed factor clock for now as there's no generic multiplier
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* clock implementation and we currently have no need to change
|
|
* the multiplier value.
|
|
*/
|
|
value = readl(base + CPG_PLL2CR);
|
|
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
|
if (cpg_quirks & PLL_ERRATA)
|
|
mult *= 2;
|
|
break;
|
|
|
|
case CLK_TYPE_GEN3_PLL3:
|
|
mult = cpg_pll_config->pll3_mult;
|
|
div = cpg_pll_config->pll3_div;
|
|
break;
|
|
|
|
case CLK_TYPE_GEN3_PLL4:
|
|
/*
|
|
* PLL4 is a configurable multiplier clock. Register it as a
|
|
* fixed factor clock for now as there's no generic multiplier
|
|
* clock implementation and we currently have no need to change
|
|
* the multiplier value.
|
|
*/
|
|
value = readl(base + CPG_PLL4CR);
|
|
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
|
if (cpg_quirks & PLL_ERRATA)
|
|
mult *= 2;
|
|
break;
|
|
|
|
case CLK_TYPE_GEN3_SD:
|
|
return cpg_sd_clk_register(core, base, __clk_get_name(parent),
|
|
notifiers);
|
|
|
|
case CLK_TYPE_GEN3_R:
|
|
if (cpg_quirks & RCKCR_CKSEL) {
|
|
struct cpg_simple_notifier *csn;
|
|
|
|
csn = kzalloc(sizeof(*csn), GFP_KERNEL);
|
|
if (!csn)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
csn->reg = base + CPG_RCKCR;
|
|
|
|
/*
|
|
* RINT is default.
|
|
* Only if EXTALR is populated, we switch to it.
|
|
*/
|
|
value = readl(csn->reg) & 0x3f;
|
|
|
|
if (clk_get_rate(clks[cpg_clk_extalr])) {
|
|
parent = clks[cpg_clk_extalr];
|
|
value |= CPG_RCKCR_CKSEL;
|
|
}
|
|
|
|
writel(value, csn->reg);
|
|
cpg_simple_notifier_register(notifiers, csn);
|
|
break;
|
|
}
|
|
|
|
/* Select parent clock of RCLK by MD28 */
|
|
if (cpg_mode & BIT(28))
|
|
parent = clks[cpg_clk_extalr];
|
|
break;
|
|
|
|
case CLK_TYPE_GEN3_MDSEL:
|
|
/*
|
|
* Clock selectable between two parents and two fixed dividers
|
|
* using a mode pin
|
|
*/
|
|
if (cpg_mode & BIT(core->offset)) {
|
|
div = core->div & 0xffff;
|
|
} else {
|
|
parent = clks[core->parent >> 16];
|
|
if (IS_ERR(parent))
|
|
return ERR_CAST(parent);
|
|
div = core->div >> 16;
|
|
}
|
|
mult = 1;
|
|
break;
|
|
|
|
case CLK_TYPE_GEN3_Z:
|
|
return cpg_z_clk_register(core->name, __clk_get_name(parent),
|
|
base, CPG_FRQCRC_ZFC_MASK);
|
|
|
|
case CLK_TYPE_GEN3_Z2:
|
|
return cpg_z_clk_register(core->name, __clk_get_name(parent),
|
|
base, CPG_FRQCRC_Z2FC_MASK);
|
|
|
|
case CLK_TYPE_GEN3_OSC:
|
|
/*
|
|
* Clock combining OSC EXTAL predivider and a fixed divider
|
|
*/
|
|
div = cpg_pll_config->osc_prediv * core->div;
|
|
break;
|
|
|
|
case CLK_TYPE_GEN3_RCKSEL:
|
|
/*
|
|
* Clock selectable between two parents and two fixed dividers
|
|
* using RCKCR.CKSEL
|
|
*/
|
|
if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
|
|
div = core->div & 0xffff;
|
|
} else {
|
|
parent = clks[core->parent >> 16];
|
|
if (IS_ERR(parent))
|
|
return ERR_CAST(parent);
|
|
div = core->div >> 16;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
return clk_register_fixed_factor(NULL, core->name,
|
|
__clk_get_name(parent), 0, mult, div);
|
|
}
|
|
|
|
int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
|
|
unsigned int clk_extalr, u32 mode)
|
|
{
|
|
const struct soc_device_attribute *attr;
|
|
|
|
cpg_pll_config = config;
|
|
cpg_clk_extalr = clk_extalr;
|
|
cpg_mode = mode;
|
|
attr = soc_device_match(cpg_quirks_match);
|
|
if (attr)
|
|
cpg_quirks = (uintptr_t)attr->data;
|
|
pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
|
|
return 0;
|
|
}
|