667 lines
17 KiB
C
667 lines
17 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_vce.h"
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#include "cikd.h"
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#include "vce/vce_2_0_d.h"
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#include "vce/vce_2_0_sh_mask.h"
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#include "oss/oss_2_0_d.h"
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#include "oss/oss_2_0_sh_mask.h"
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#define VCE_V2_0_FW_SIZE (256 * 1024)
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#define VCE_V2_0_STACK_SIZE (64 * 1024)
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#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
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static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
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static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
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static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
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/**
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* vce_v2_0_ring_get_rptr - get read pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware read pointer
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*/
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static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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return RREG32(mmVCE_RB_RPTR);
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else
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return RREG32(mmVCE_RB_RPTR2);
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}
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/**
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* vce_v2_0_ring_get_wptr - get write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Returns the current hardware write pointer
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*/
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static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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return RREG32(mmVCE_RB_WPTR);
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else
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return RREG32(mmVCE_RB_WPTR2);
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}
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/**
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* vce_v2_0_ring_set_wptr - set write pointer
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*
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* @ring: amdgpu_ring pointer
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*
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* Commits the write pointer to the hardware
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*/
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static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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if (ring == &adev->vce.ring[0])
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WREG32(mmVCE_RB_WPTR, ring->wptr);
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else
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WREG32(mmVCE_RB_WPTR2, ring->wptr);
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}
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/**
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* vce_v2_0_start - start VCE block
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*
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* @adev: amdgpu_device pointer
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*
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* Setup and start the VCE block
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*/
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static int vce_v2_0_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring;
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int i, j, r;
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vce_v2_0_mc_resume(adev);
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/* set BUSY flag */
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WREG32_P(mmVCE_STATUS, 1, ~1);
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ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, ring->wptr);
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WREG32(mmVCE_RB_WPTR, ring->wptr);
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WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
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ring = &adev->vce.ring[1];
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WREG32(mmVCE_RB_RPTR2, ring->wptr);
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WREG32(mmVCE_RB_WPTR2, ring->wptr);
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WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
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WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
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WREG32_P(mmVCE_SOFT_RESET,
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VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(100);
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WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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for (i = 0; i < 10; ++i) {
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uint32_t status;
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for (j = 0; j < 100; ++j) {
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status = RREG32(mmVCE_STATUS);
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if (status & 2)
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break;
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mdelay(10);
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}
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r = 0;
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if (status & 2)
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break;
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DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
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WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(10);
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WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(10);
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r = -1;
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}
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/* clear BUSY flag */
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WREG32_P(mmVCE_STATUS, 0, ~1);
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if (r) {
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DRM_ERROR("VCE not responding, giving up!!!\n");
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return r;
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}
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return 0;
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}
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static int vce_v2_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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vce_v2_0_set_ring_funcs(adev);
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vce_v2_0_set_irq_funcs(adev);
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return 0;
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}
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static int vce_v2_0_sw_init(void *handle)
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{
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struct amdgpu_ring *ring;
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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/* VCE */
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r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
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if (r)
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return r;
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r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
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VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
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if (r)
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return r;
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r = amdgpu_vce_resume(adev);
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if (r)
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return r;
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ring = &adev->vce.ring[0];
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sprintf(ring->name, "vce0");
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r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
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&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
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if (r)
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return r;
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ring = &adev->vce.ring[1];
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sprintf(ring->name, "vce1");
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r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
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&adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
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if (r)
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return r;
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return r;
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}
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static int vce_v2_0_sw_fini(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = amdgpu_vce_suspend(adev);
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if (r)
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return r;
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r = amdgpu_vce_sw_fini(adev);
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if (r)
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return r;
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return r;
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}
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static int vce_v2_0_hw_init(void *handle)
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{
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struct amdgpu_ring *ring;
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = vce_v2_0_start(adev);
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if (r)
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return r;
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ring = &adev->vce.ring[0];
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ring->ready = true;
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r = amdgpu_ring_test_ring(ring);
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if (r) {
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ring->ready = false;
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return r;
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}
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ring = &adev->vce.ring[1];
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ring->ready = true;
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r = amdgpu_ring_test_ring(ring);
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if (r) {
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ring->ready = false;
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return r;
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}
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DRM_INFO("VCE initialized successfully.\n");
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return 0;
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}
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static int vce_v2_0_hw_fini(void *handle)
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{
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return 0;
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}
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static int vce_v2_0_suspend(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = vce_v2_0_hw_fini(adev);
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if (r)
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return r;
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r = amdgpu_vce_suspend(adev);
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if (r)
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return r;
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return r;
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}
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static int vce_v2_0_resume(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = amdgpu_vce_resume(adev);
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if (r)
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return r;
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r = vce_v2_0_hw_init(adev);
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if (r)
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return r;
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return r;
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}
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static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
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{
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u32 tmp;
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if (gated) {
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0xe70000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp |= 0xff000000;
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3fc;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
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} else {
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0xe7;
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tmp &= ~0xe70000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp |= 0x1fe000;
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tmp &= ~0xff000000;
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp |= 0x3fc;
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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}
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}
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static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
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{
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u32 orig, tmp;
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp &= ~0x00060006;
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if (gated) {
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tmp |= 0xe10000;
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} else {
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tmp |= 0xe1;
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tmp &= ~0xe10000;
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}
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp &= ~0x1fe000;
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tmp &= ~0xff000000;
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if (tmp != orig)
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3fc;
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if (tmp != orig)
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WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
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if (gated)
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
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}
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static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
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{
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WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
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}
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static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
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{
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bool sw_cg = false;
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
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if (sw_cg)
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vce_v2_0_set_sw_cg(adev, true);
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else
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vce_v2_0_set_dyn_cg(adev, true);
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} else {
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vce_v2_0_disable_cg(adev);
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if (sw_cg)
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vce_v2_0_set_sw_cg(adev, false);
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else
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vce_v2_0_set_dyn_cg(adev, false);
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}
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}
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static void vce_v2_0_init_cg(struct amdgpu_device *adev)
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{
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u32 tmp;
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tmp = RREG32(mmVCE_CLOCK_GATING_A);
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tmp &= ~0xfff;
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tmp |= ((0 << 0) | (4 << 4));
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tmp |= 0x40000;
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WREG32(mmVCE_CLOCK_GATING_A, tmp);
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tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
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tmp &= ~0xfff;
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tmp |= ((0 << 0) | (4 << 4));
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WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(mmVCE_CLOCK_GATING_B);
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tmp |= 0x10;
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tmp &= ~0x100000;
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WREG32(mmVCE_CLOCK_GATING_B, tmp);
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}
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static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
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{
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uint64_t addr = adev->vce.gpu_addr;
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uint32_t size;
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WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
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WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
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WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
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WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
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WREG32(mmVCE_LMI_CTRL, 0x00398000);
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WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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WREG32(mmVCE_LMI_SWAP_CNTL, 0);
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WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
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WREG32(mmVCE_LMI_VM_CTRL, 0);
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addr += AMDGPU_VCE_FIRMWARE_OFFSET;
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size = VCE_V2_0_FW_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = VCE_V2_0_STACK_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = VCE_V2_0_DATA_SIZE;
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WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
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WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
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WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
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WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
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~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
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vce_v2_0_init_cg(adev);
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}
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static bool vce_v2_0_is_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
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}
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static int vce_v2_0_wait_for_idle(void *handle)
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{
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unsigned i;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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for (i = 0; i < adev->usec_timeout; i++) {
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if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
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return 0;
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}
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return -ETIMEDOUT;
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}
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static int vce_v2_0_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
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~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
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mdelay(5);
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return vce_v2_0_start(adev);
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}
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static void vce_v2_0_print_status(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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dev_info(adev->dev, "VCE 2.0 registers\n");
|
|
dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
|
|
RREG32(mmVCE_STATUS));
|
|
dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n",
|
|
RREG32(mmVCE_VCPU_CNTL));
|
|
dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
|
|
RREG32(mmVCE_VCPU_CACHE_OFFSET0));
|
|
dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
|
|
RREG32(mmVCE_VCPU_CACHE_SIZE0));
|
|
dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
|
|
RREG32(mmVCE_VCPU_CACHE_OFFSET1));
|
|
dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
|
|
RREG32(mmVCE_VCPU_CACHE_SIZE1));
|
|
dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
|
|
RREG32(mmVCE_VCPU_CACHE_OFFSET2));
|
|
dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
|
|
RREG32(mmVCE_VCPU_CACHE_SIZE2));
|
|
dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n",
|
|
RREG32(mmVCE_SOFT_RESET));
|
|
dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n",
|
|
RREG32(mmVCE_RB_BASE_LO2));
|
|
dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n",
|
|
RREG32(mmVCE_RB_BASE_HI2));
|
|
dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n",
|
|
RREG32(mmVCE_RB_SIZE2));
|
|
dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n",
|
|
RREG32(mmVCE_RB_RPTR2));
|
|
dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n",
|
|
RREG32(mmVCE_RB_WPTR2));
|
|
dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n",
|
|
RREG32(mmVCE_RB_BASE_LO));
|
|
dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n",
|
|
RREG32(mmVCE_RB_BASE_HI));
|
|
dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n",
|
|
RREG32(mmVCE_RB_SIZE));
|
|
dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n",
|
|
RREG32(mmVCE_RB_RPTR));
|
|
dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n",
|
|
RREG32(mmVCE_RB_WPTR));
|
|
dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n",
|
|
RREG32(mmVCE_CLOCK_GATING_A));
|
|
dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n",
|
|
RREG32(mmVCE_CLOCK_GATING_B));
|
|
dev_info(adev->dev, " VCE_CGTT_CLK_OVERRIDE=0x%08X\n",
|
|
RREG32(mmVCE_CGTT_CLK_OVERRIDE));
|
|
dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n",
|
|
RREG32(mmVCE_UENC_CLOCK_GATING));
|
|
dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
|
|
RREG32(mmVCE_UENC_REG_CLOCK_GATING));
|
|
dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n",
|
|
RREG32(mmVCE_SYS_INT_EN));
|
|
dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n",
|
|
RREG32(mmVCE_LMI_CTRL2));
|
|
dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n",
|
|
RREG32(mmVCE_LMI_CTRL));
|
|
dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n",
|
|
RREG32(mmVCE_LMI_VM_CTRL));
|
|
dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n",
|
|
RREG32(mmVCE_LMI_SWAP_CNTL));
|
|
dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
|
|
RREG32(mmVCE_LMI_SWAP_CNTL1));
|
|
dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n",
|
|
RREG32(mmVCE_LMI_CACHE_CTRL));
|
|
}
|
|
|
|
static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *source,
|
|
unsigned type,
|
|
enum amdgpu_interrupt_state state)
|
|
{
|
|
uint32_t val = 0;
|
|
|
|
if (state == AMDGPU_IRQ_STATE_ENABLE)
|
|
val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
|
|
|
|
WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
|
|
return 0;
|
|
}
|
|
|
|
static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
|
|
struct amdgpu_irq_src *source,
|
|
struct amdgpu_iv_entry *entry)
|
|
{
|
|
DRM_DEBUG("IH: VCE\n");
|
|
switch (entry->src_data) {
|
|
case 0:
|
|
amdgpu_fence_process(&adev->vce.ring[0]);
|
|
break;
|
|
case 1:
|
|
amdgpu_fence_process(&adev->vce.ring[1]);
|
|
break;
|
|
default:
|
|
DRM_ERROR("Unhandled interrupt: %d %d\n",
|
|
entry->src_id, entry->src_data);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vce_v2_0_set_clockgating_state(void *handle,
|
|
enum amd_clockgating_state state)
|
|
{
|
|
bool gate = false;
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
if (state == AMD_CG_STATE_GATE)
|
|
gate = true;
|
|
|
|
vce_v2_0_enable_mgcg(adev, gate);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vce_v2_0_set_powergating_state(void *handle,
|
|
enum amd_powergating_state state)
|
|
{
|
|
/* This doesn't actually powergate the VCE block.
|
|
* That's done in the dpm code via the SMC. This
|
|
* just re-inits the block as necessary. The actual
|
|
* gating still happens in the dpm code. We should
|
|
* revisit this when there is a cleaner line between
|
|
* the smc and the hw blocks
|
|
*/
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
|
|
|
if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
|
|
return 0;
|
|
|
|
if (state == AMD_PG_STATE_GATE)
|
|
/* XXX do we need a vce_v2_0_stop()? */
|
|
return 0;
|
|
else
|
|
return vce_v2_0_start(adev);
|
|
}
|
|
|
|
const struct amd_ip_funcs vce_v2_0_ip_funcs = {
|
|
.early_init = vce_v2_0_early_init,
|
|
.late_init = NULL,
|
|
.sw_init = vce_v2_0_sw_init,
|
|
.sw_fini = vce_v2_0_sw_fini,
|
|
.hw_init = vce_v2_0_hw_init,
|
|
.hw_fini = vce_v2_0_hw_fini,
|
|
.suspend = vce_v2_0_suspend,
|
|
.resume = vce_v2_0_resume,
|
|
.is_idle = vce_v2_0_is_idle,
|
|
.wait_for_idle = vce_v2_0_wait_for_idle,
|
|
.soft_reset = vce_v2_0_soft_reset,
|
|
.print_status = vce_v2_0_print_status,
|
|
.set_clockgating_state = vce_v2_0_set_clockgating_state,
|
|
.set_powergating_state = vce_v2_0_set_powergating_state,
|
|
};
|
|
|
|
static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
|
|
.get_rptr = vce_v2_0_ring_get_rptr,
|
|
.get_wptr = vce_v2_0_ring_get_wptr,
|
|
.set_wptr = vce_v2_0_ring_set_wptr,
|
|
.parse_cs = amdgpu_vce_ring_parse_cs,
|
|
.emit_ib = amdgpu_vce_ring_emit_ib,
|
|
.emit_fence = amdgpu_vce_ring_emit_fence,
|
|
.test_ring = amdgpu_vce_ring_test_ring,
|
|
.test_ib = amdgpu_vce_ring_test_ib,
|
|
.insert_nop = amdgpu_ring_insert_nop,
|
|
.pad_ib = amdgpu_ring_generic_pad_ib,
|
|
};
|
|
|
|
static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
|
|
{
|
|
adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs;
|
|
adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs;
|
|
}
|
|
|
|
static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
|
|
.set = vce_v2_0_set_interrupt_state,
|
|
.process = vce_v2_0_process_interrupt,
|
|
};
|
|
|
|
static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
|
|
{
|
|
adev->vce.irq.num_types = 1;
|
|
adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
|
|
};
|