675 lines
20 KiB
C
675 lines
20 KiB
C
/*
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* linux/drivers/ide/pci/piix.c Version 0.44 March 20, 2003
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*
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* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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* PIO mode setting function for Intel chipsets.
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* For use instead of BIOS settings.
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*
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* 40-41
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* 42-43
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*
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* 41
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* 43
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*
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* | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
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* | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
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* | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
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* | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
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*
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* sitre = word40 & 0x4000; primary
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* sitre = word42 & 0x4000; secondary
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*
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* 44 8421|8421 hdd|hdb
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*
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* 48 8421 hdd|hdc|hdb|hda udma enabled
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*
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* 0001 hda
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* 0010 hdb
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* 0100 hdc
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* 1000 hdd
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*
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* 4a 84|21 hdb|hda
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* 4b 84|21 hdd|hdc
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*
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* ata-33/82371AB
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* ata-33/82371EB
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* ata-33/82801AB ata-66/82801AA
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* 00|00 udma 0 00|00 reserved
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* 01|01 udma 1 01|01 udma 3
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* 10|10 udma 2 10|10 udma 4
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* 11|11 reserved 11|11 reserved
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*
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* 54 8421|8421 ata66 drive|ata66 enable
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*
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* pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
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* pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
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* pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
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* pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
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* pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
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* pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
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*
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* Documentation
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* Publically available from Intel web site. Errata documentation
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* is also publically available. As an aide to anyone hacking on this
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* driver the list of errata that are relevant is below.going back to
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* PIIX4. Older device documentation is now a bit tricky to find.
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*
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* Errata of note:
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*
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* Unfixable
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* PIIX4 errata #9 - Only on ultra obscure hw
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* ICH3 errata #13 - Not observed to affect real hw
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* by Intel
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*
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* Things we must deal with
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* PIIX4 errata #10 - BM IDE hang with non UDMA
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* (must stop/start dma to recover)
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* 440MX errata #15 - As PIIX4 errata #10
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* PIIX4 errata #15 - Must not read control registers
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* during a PIO transfer
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* 440MX errata #13 - As PIIX4 errata #15
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* ICH2 errata #21 - DMA mode 0 doesn't work right
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* ICH0/1 errata #55 - As ICH2 errata #21
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* ICH2 spec c #9 - Extra operations needed to handle
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* drive hotswap [NOT YET SUPPORTED]
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* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
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* and must be dword aligned
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* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
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*
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* Should have been BIOS fixed:
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* 450NX: errata #19 - DMA hangs on old 450NX
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* 450NX: errata #20 - DMA hangs on old 450NX
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* 450NX: errata #25 - Corruption with DMA on old 450NX
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* ICH3 errata #15 - IDE deadlock under high load
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* (BIOS must set dev 31 fn 0 bit 23)
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* ICH3 errata #18 - Don't use native mode
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <asm/io.h>
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static int no_piix_dma;
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/**
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* piix_ratemask - compute rate mask for PIIX IDE
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* @drive: IDE drive to compute for
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*
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* Returns the available modes for the PIIX IDE controller.
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*/
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static u8 piix_ratemask (ide_drive_t *drive)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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u8 mode;
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switch(dev->device) {
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case PCI_DEVICE_ID_INTEL_82801EB_1:
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mode = 3;
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break;
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/* UDMA 100 capable */
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case PCI_DEVICE_ID_INTEL_82801BA_8:
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case PCI_DEVICE_ID_INTEL_82801BA_9:
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case PCI_DEVICE_ID_INTEL_82801CA_10:
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case PCI_DEVICE_ID_INTEL_82801CA_11:
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case PCI_DEVICE_ID_INTEL_82801E_11:
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case PCI_DEVICE_ID_INTEL_82801DB_1:
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case PCI_DEVICE_ID_INTEL_82801DB_10:
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case PCI_DEVICE_ID_INTEL_82801DB_11:
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case PCI_DEVICE_ID_INTEL_82801EB_11:
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case PCI_DEVICE_ID_INTEL_ESB_2:
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case PCI_DEVICE_ID_INTEL_ICH6_19:
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case PCI_DEVICE_ID_INTEL_ICH7_21:
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case PCI_DEVICE_ID_INTEL_ESB2_18:
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mode = 3;
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break;
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/* UDMA 66 capable */
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case PCI_DEVICE_ID_INTEL_82801AA_1:
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case PCI_DEVICE_ID_INTEL_82372FB_1:
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mode = 2;
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break;
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/* UDMA 33 capable */
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case PCI_DEVICE_ID_INTEL_82371AB:
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case PCI_DEVICE_ID_INTEL_82443MX_1:
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case PCI_DEVICE_ID_INTEL_82451NX:
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case PCI_DEVICE_ID_INTEL_82801AB_1:
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return 1;
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/* Non UDMA capable (MWDMA2) */
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case PCI_DEVICE_ID_INTEL_82371SB_1:
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case PCI_DEVICE_ID_INTEL_82371FB_1:
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case PCI_DEVICE_ID_INTEL_82371FB_0:
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case PCI_DEVICE_ID_INTEL_82371MX:
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default:
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return 0;
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}
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/*
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* If we are UDMA66 capable fall back to UDMA33
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* if the drive cannot see an 80pin cable.
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*/
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if (!eighty_ninty_three(drive))
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mode = min(mode, (u8)1);
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return mode;
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}
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/**
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* piix_dma_2_pio - return the PIO mode matching DMA
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* @xfer_rate: transfer speed
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*
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* Returns the nearest equivalent PIO timing for the PIO or DMA
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* mode requested by the controller.
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*/
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static u8 piix_dma_2_pio (u8 xfer_rate) {
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switch(xfer_rate) {
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case XFER_UDMA_6:
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case XFER_UDMA_5:
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case XFER_UDMA_4:
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case XFER_UDMA_3:
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case XFER_UDMA_2:
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case XFER_UDMA_1:
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case XFER_UDMA_0:
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case XFER_MW_DMA_2:
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case XFER_PIO_4:
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return 4;
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case XFER_MW_DMA_1:
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case XFER_PIO_3:
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return 3;
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case XFER_SW_DMA_2:
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case XFER_PIO_2:
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return 2;
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case XFER_MW_DMA_0:
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case XFER_SW_DMA_1:
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case XFER_SW_DMA_0:
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case XFER_PIO_1:
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case XFER_PIO_0:
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case XFER_PIO_SLOW:
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default:
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return 0;
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}
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}
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/**
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* piix_tune_drive - tune a drive attached to a PIIX
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* @drive: drive to tune
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* @pio: desired PIO mode
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*
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* Set the interface PIO mode based upon the settings done by AMI BIOS
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* (might be useful if drive is not registered in CMOS for any reason).
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*/
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static void piix_tune_drive (ide_drive_t *drive, u8 pio)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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int is_slave = (&hwif->drives[1] == drive);
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int master_port = hwif->channel ? 0x42 : 0x40;
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int slave_port = 0x44;
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unsigned long flags;
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u16 master_data;
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u8 slave_data;
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/* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
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spin_lock_irqsave(&ide_lock, flags);
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pci_read_config_word(dev, master_port, &master_data);
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if (is_slave) {
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master_data = master_data | 0x4000;
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if (pio > 1)
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/* enable PPE, IE and TIME */
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master_data = master_data | 0x0070;
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pci_read_config_byte(dev, slave_port, &slave_data);
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slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
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slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
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} else {
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master_data = master_data & 0xccf8;
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if (pio > 1)
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/* enable PPE, IE and TIME */
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master_data = master_data | 0x0007;
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master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
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}
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pci_write_config_word(dev, master_port, master_data);
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if (is_slave)
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pci_write_config_byte(dev, slave_port, slave_data);
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spin_unlock_irqrestore(&ide_lock, flags);
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}
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/**
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* piix_tune_chipset - tune a PIIX interface
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* @drive: IDE drive to tune
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* @xferspeed: speed to configure
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*
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* Set a PIIX interface channel to the desired speeds. This involves
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* requires the right timing data into the PIIX configuration space
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* then setting the drive parameters appropriately
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*/
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static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 maslave = hwif->channel ? 0x42 : 0x40;
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u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed);
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int a_speed = 3 << (drive->dn * 4);
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int u_flag = 1 << drive->dn;
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int v_flag = 0x01 << drive->dn;
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int w_flag = 0x10 << drive->dn;
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int u_speed = 0;
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int sitre;
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u16 reg4042, reg4a;
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u8 reg48, reg54, reg55;
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pci_read_config_word(dev, maslave, ®4042);
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sitre = (reg4042 & 0x4000) ? 1 : 0;
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pci_read_config_byte(dev, 0x48, ®48);
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pci_read_config_word(dev, 0x4a, ®4a);
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pci_read_config_byte(dev, 0x54, ®54);
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pci_read_config_byte(dev, 0x55, ®55);
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switch(speed) {
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case XFER_UDMA_4:
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case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
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case XFER_UDMA_5:
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case XFER_UDMA_3:
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case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
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case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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case XFER_SW_DMA_2: break;
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case XFER_PIO_4:
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case XFER_PIO_3:
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case XFER_PIO_2:
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case XFER_PIO_0: break;
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default: return -1;
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}
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if (speed >= XFER_UDMA_0) {
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if (!(reg48 & u_flag))
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pci_write_config_byte(dev, 0x48, reg48 | u_flag);
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if (speed == XFER_UDMA_5) {
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pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
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} else {
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pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
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}
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if ((reg4a & a_speed) != u_speed)
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pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
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if (speed > XFER_UDMA_2) {
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if (!(reg54 & v_flag))
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pci_write_config_byte(dev, 0x54, reg54 | v_flag);
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} else
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pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
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} else {
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if (reg48 & u_flag)
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pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
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if (reg4a & a_speed)
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pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
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if (reg54 & v_flag)
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pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
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if (reg55 & w_flag)
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pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
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}
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piix_tune_drive(drive, piix_dma_2_pio(speed));
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return (ide_config_drive_speed(drive, speed));
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}
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/**
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* piix_faulty_dma0 - check for DMA0 errata
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* @hwif: IDE interface to check
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*
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* If an ICH/ICH0/ICH2 interface is is operating in multi-word
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* DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
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* inadvertently provide an extra piece of secondary data to the primary
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* device resulting in data corruption.
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*
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* With such a device this test function returns true. This allows
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* our tuning code to follow Intel recommendations and use PIO on
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* such devices.
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*/
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static int piix_faulty_dma0(ide_hwif_t *hwif)
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{
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switch(hwif->pci_dev->device)
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{
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case PCI_DEVICE_ID_INTEL_82801AA_1: /* ICH */
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case PCI_DEVICE_ID_INTEL_82801AB_1: /* ICH0 */
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case PCI_DEVICE_ID_INTEL_82801BA_8: /* ICH2 */
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case PCI_DEVICE_ID_INTEL_82801BA_9: /* ICH2 */
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return 1;
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}
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return 0;
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}
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/**
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* piix_config_drive_for_dma - configure drive for DMA
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* @drive: IDE drive to configure
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*
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* Set up a PIIX interface channel for the best available speed.
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* We prefer UDMA if it is available and then MWDMA. If DMA is
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* not available we switch to PIO and return 0.
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*/
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static int piix_config_drive_for_dma (ide_drive_t *drive)
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{
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u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
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/* Some ICH devices cannot support DMA mode 0 */
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if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
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speed = 0;
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/* If no DMA speed was available or the chipset has DMA bugs
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then disable DMA and use PIO */
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if (!speed || no_piix_dma) {
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u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
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speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
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}
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(void) piix_tune_chipset(drive, speed);
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return ide_dma_enable(drive);
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}
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/**
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* piix_config_drive_xfer_rate - set up an IDE device
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* @drive: IDE drive to configure
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*
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* Set up the PIIX interface for the best available speed on this
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* interface, preferring DMA to PIO.
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*/
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static int piix_config_drive_xfer_rate (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct hd_driveid *id = drive->id;
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drive->init_speed = 0;
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if ((id->capability & 1) && drive->autodma) {
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if (ide_use_dma(drive)) {
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if (piix_config_drive_for_dma(drive))
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return hwif->ide_dma_on(drive);
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}
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goto fast_ata_pio;
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} else if ((id->capability & 8) || (id->field_valid & 2)) {
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fast_ata_pio:
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/* Find best PIO mode. */
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hwif->tuneproc(drive, 255);
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return hwif->ide_dma_off_quietly(drive);
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}
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/* IORDY not supported */
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return 0;
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}
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/**
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* init_chipset_piix - set up the PIIX chipset
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* @dev: PCI device to set up
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* @name: Name of the device
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*
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* Initialize the PCI device as required. For the PIIX this turns
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* out to be nice and simple
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*/
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static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
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{
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switch(dev->device) {
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case PCI_DEVICE_ID_INTEL_82801EB_1:
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case PCI_DEVICE_ID_INTEL_82801AA_1:
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case PCI_DEVICE_ID_INTEL_82801AB_1:
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case PCI_DEVICE_ID_INTEL_82801BA_8:
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case PCI_DEVICE_ID_INTEL_82801BA_9:
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case PCI_DEVICE_ID_INTEL_82801CA_10:
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case PCI_DEVICE_ID_INTEL_82801CA_11:
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case PCI_DEVICE_ID_INTEL_82801DB_1:
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case PCI_DEVICE_ID_INTEL_82801DB_10:
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case PCI_DEVICE_ID_INTEL_82801DB_11:
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case PCI_DEVICE_ID_INTEL_82801EB_11:
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case PCI_DEVICE_ID_INTEL_82801E_11:
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case PCI_DEVICE_ID_INTEL_ESB_2:
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case PCI_DEVICE_ID_INTEL_ICH6_19:
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case PCI_DEVICE_ID_INTEL_ICH7_21:
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case PCI_DEVICE_ID_INTEL_ESB2_18:
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{
|
|
unsigned int extra = 0;
|
|
pci_read_config_dword(dev, 0x54, &extra);
|
|
pci_write_config_dword(dev, 0x54, extra|0x400);
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* init_hwif_piix - fill in the hwif for the PIIX
|
|
* @hwif: IDE interface
|
|
*
|
|
* Set up the ide_hwif_t for the PIIX interface according to the
|
|
* capabilities of the hardware.
|
|
*/
|
|
|
|
static void __devinit init_hwif_piix(ide_hwif_t *hwif)
|
|
{
|
|
u8 reg54h = 0, reg55h = 0, ata66 = 0;
|
|
u8 mask = hwif->channel ? 0xc0 : 0x30;
|
|
|
|
#ifndef CONFIG_IA64
|
|
if (!hwif->irq)
|
|
hwif->irq = hwif->channel ? 15 : 14;
|
|
#endif /* CONFIG_IA64 */
|
|
|
|
if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
|
|
/* This is a painful system best to let it self tune for now */
|
|
return;
|
|
}
|
|
|
|
hwif->autodma = 0;
|
|
hwif->tuneproc = &piix_tune_drive;
|
|
hwif->speedproc = &piix_tune_chipset;
|
|
hwif->drives[0].autotune = 1;
|
|
hwif->drives[1].autotune = 1;
|
|
|
|
if (!hwif->dma_base)
|
|
return;
|
|
|
|
hwif->atapi_dma = 1;
|
|
hwif->ultra_mask = 0x3f;
|
|
hwif->mwdma_mask = 0x06;
|
|
hwif->swdma_mask = 0x04;
|
|
|
|
switch(hwif->pci_dev->device) {
|
|
case PCI_DEVICE_ID_INTEL_82371MX:
|
|
hwif->mwdma_mask = 0x80;
|
|
hwif->swdma_mask = 0x80;
|
|
case PCI_DEVICE_ID_INTEL_82371FB_0:
|
|
case PCI_DEVICE_ID_INTEL_82371FB_1:
|
|
case PCI_DEVICE_ID_INTEL_82371SB_1:
|
|
hwif->ultra_mask = 0x80;
|
|
break;
|
|
case PCI_DEVICE_ID_INTEL_82371AB:
|
|
case PCI_DEVICE_ID_INTEL_82443MX_1:
|
|
case PCI_DEVICE_ID_INTEL_82451NX:
|
|
case PCI_DEVICE_ID_INTEL_82801AB_1:
|
|
hwif->ultra_mask = 0x07;
|
|
break;
|
|
default:
|
|
pci_read_config_byte(hwif->pci_dev, 0x54, ®54h);
|
|
pci_read_config_byte(hwif->pci_dev, 0x55, ®55h);
|
|
ata66 = (reg54h & mask) ? 1 : 0;
|
|
break;
|
|
}
|
|
|
|
if (!(hwif->udma_four))
|
|
hwif->udma_four = ata66;
|
|
hwif->ide_dma_check = &piix_config_drive_xfer_rate;
|
|
if (!noautodma)
|
|
hwif->autodma = 1;
|
|
|
|
hwif->drives[1].autodma = hwif->autodma;
|
|
hwif->drives[0].autodma = hwif->autodma;
|
|
}
|
|
|
|
#define DECLARE_PIIX_DEV(name_str) \
|
|
{ \
|
|
.name = name_str, \
|
|
.init_chipset = init_chipset_piix, \
|
|
.init_hwif = init_hwif_piix, \
|
|
.channels = 2, \
|
|
.autodma = AUTODMA, \
|
|
.enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
|
|
.bootable = ON_BOARD, \
|
|
}
|
|
|
|
static ide_pci_device_t piix_pci_info[] __devinitdata = {
|
|
/* 0 */ DECLARE_PIIX_DEV("PIIXa"),
|
|
/* 1 */ DECLARE_PIIX_DEV("PIIXb"),
|
|
|
|
{ /* 2 */
|
|
.name = "MPIIX",
|
|
.init_hwif = init_hwif_piix,
|
|
.channels = 2,
|
|
.autodma = NODMA,
|
|
.enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}},
|
|
.bootable = ON_BOARD,
|
|
},
|
|
|
|
/* 3 */ DECLARE_PIIX_DEV("PIIX3"),
|
|
/* 4 */ DECLARE_PIIX_DEV("PIIX4"),
|
|
/* 5 */ DECLARE_PIIX_DEV("ICH0"),
|
|
/* 6 */ DECLARE_PIIX_DEV("PIIX4"),
|
|
/* 7 */ DECLARE_PIIX_DEV("ICH"),
|
|
/* 8 */ DECLARE_PIIX_DEV("PIIX4"),
|
|
/* 9 */ DECLARE_PIIX_DEV("PIIX4"),
|
|
/* 10 */ DECLARE_PIIX_DEV("ICH2"),
|
|
/* 11 */ DECLARE_PIIX_DEV("ICH2M"),
|
|
/* 12 */ DECLARE_PIIX_DEV("ICH3M"),
|
|
/* 13 */ DECLARE_PIIX_DEV("ICH3"),
|
|
/* 14 */ DECLARE_PIIX_DEV("ICH4"),
|
|
/* 15 */ DECLARE_PIIX_DEV("ICH5"),
|
|
/* 16 */ DECLARE_PIIX_DEV("C-ICH"),
|
|
/* 17 */ DECLARE_PIIX_DEV("ICH4"),
|
|
/* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"),
|
|
/* 19 */ DECLARE_PIIX_DEV("ICH5"),
|
|
/* 20 */ DECLARE_PIIX_DEV("ICH6"),
|
|
/* 21 */ DECLARE_PIIX_DEV("ICH7"),
|
|
/* 22 */ DECLARE_PIIX_DEV("ICH4"),
|
|
/* 23 */ DECLARE_PIIX_DEV("ESB2"),
|
|
};
|
|
|
|
/**
|
|
* piix_init_one - called when a PIIX is found
|
|
* @dev: the piix device
|
|
* @id: the matching pci id
|
|
*
|
|
* Called when the PCI registration layer (or the IDE initialization)
|
|
* finds a device matching our IDE device tables.
|
|
*/
|
|
|
|
static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
ide_pci_device_t *d = &piix_pci_info[id->driver_data];
|
|
|
|
return ide_setup_pci_device(dev, d);
|
|
}
|
|
|
|
/**
|
|
* piix_check_450nx - Check for problem 450NX setup
|
|
*
|
|
* Check for the present of 450NX errata #19 and errata #25. If
|
|
* they are found, disable use of DMA IDE
|
|
*/
|
|
|
|
static void __devinit piix_check_450nx(void)
|
|
{
|
|
struct pci_dev *pdev = NULL;
|
|
u16 cfg;
|
|
u8 rev;
|
|
while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
|
|
{
|
|
/* Look for 450NX PXB. Check for problem configurations
|
|
A PCI quirk checks bit 6 already */
|
|
pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
|
|
pci_read_config_word(pdev, 0x41, &cfg);
|
|
/* Only on the original revision: IDE DMA can hang */
|
|
if(rev == 0x00)
|
|
no_piix_dma = 1;
|
|
/* On all revisions below 5 PXB bus lock must be disabled for IDE */
|
|
else if(cfg & (1<<14) && rev < 5)
|
|
no_piix_dma = 2;
|
|
}
|
|
if(no_piix_dma)
|
|
printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
|
|
if(no_piix_dma == 2)
|
|
printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
|
|
}
|
|
|
|
static struct pci_device_id piix_pci_tbl[] = {
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
|
|
#ifdef CONFIG_BLK_DEV_IDE_SATA
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
|
|
#endif
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
|
|
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23},
|
|
{ 0, },
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
|
|
|
|
static struct pci_driver driver = {
|
|
.name = "PIIX_IDE",
|
|
.id_table = piix_pci_tbl,
|
|
.probe = piix_init_one,
|
|
};
|
|
|
|
static int __init piix_ide_init(void)
|
|
{
|
|
piix_check_450nx();
|
|
return ide_pci_register_driver(&driver);
|
|
}
|
|
|
|
module_init(piix_ide_init);
|
|
|
|
MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
|
|
MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
|
|
MODULE_LICENSE("GPL");
|