74 lines
3.0 KiB
C
74 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) STMicroelectronics 2016
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* Author: Benjamin Gaignard <benjamin.gaignard@st.com>
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*/
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#ifndef _LINUX_STM32_GPTIMER_H_
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#define _LINUX_STM32_GPTIMER_H_
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#define TIM_CR1 0x00 /* Control Register 1 */
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#define TIM_CR2 0x04 /* Control Register 2 */
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#define TIM_SMCR 0x08 /* Slave mode control reg */
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#define TIM_DIER 0x0C /* DMA/interrupt register */
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#define TIM_SR 0x10 /* Status register */
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#define TIM_EGR 0x14 /* Event Generation Reg */
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#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
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#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
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#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
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#define TIM_CNT 0x24 /* Counter */
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#define TIM_PSC 0x28 /* Prescaler */
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#define TIM_ARR 0x2c /* Auto-Reload Register */
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#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
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#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
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#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
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#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
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#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
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#define TIM_CR1_CEN BIT(0) /* Counter Enable */
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#define TIM_CR1_DIR BIT(4) /* Counter Direction */
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#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
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#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
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#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
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#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
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#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
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#define TIM_DIER_UIE BIT(0) /* Update interrupt */
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#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
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#define TIM_EGR_UG BIT(0) /* Update Generation */
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#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
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#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
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#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
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#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
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#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
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#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
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#define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */
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#define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */
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#define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */
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#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
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#define TIM_BDTR_BKE BIT(12) /* Break input enable */
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#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
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#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
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#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
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#define TIM_BDTR_BKF (BIT(16) | BIT(17) | BIT(18) | BIT(19))
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#define TIM_BDTR_BK2F (BIT(20) | BIT(21) | BIT(22) | BIT(23))
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#define TIM_BDTR_BK2E BIT(24) /* Break 2 input enable */
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#define TIM_BDTR_BK2P BIT(25) /* Break 2 input polarity */
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#define MAX_TIM_PSC 0xFFFF
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#define TIM_CR2_MMS_SHIFT 4
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#define TIM_CR2_MMS2_SHIFT 20
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#define TIM_SMCR_TS_SHIFT 4
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#define TIM_BDTR_BKF_MASK 0xF
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#define TIM_BDTR_BKF_SHIFT 16
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#define TIM_BDTR_BK2F_SHIFT 20
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struct stm32_timers {
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struct clk *clk;
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struct regmap *regmap;
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u32 max_arr;
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};
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#endif
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