247 lines
6.1 KiB
C
247 lines
6.1 KiB
C
/*
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* linux/arch/arm/mach-at91/irq.c
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*
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* Copyright (C) 2004 SAN People
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* Copyright (C) 2004 ATMEL
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* Copyright (C) Rick Bronson
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/err.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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void __iomem *at91_aic_base;
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static struct irq_domain *at91_aic_domain;
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static struct device_node *at91_aic_np;
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static void at91_aic_mask_irq(struct irq_data *d)
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{
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/* Disable interrupt on AIC */
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at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
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}
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static void at91_aic_unmask_irq(struct irq_data *d)
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{
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/* Enable interrupt on AIC */
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at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
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}
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unsigned int at91_extern_irq;
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#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
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static int at91_aic_set_type(struct irq_data *d, unsigned type)
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{
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unsigned int smr, srctype;
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
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srctype = AT91_AIC_SRCTYPE_HIGH;
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break;
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case IRQ_TYPE_EDGE_RISING:
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srctype = AT91_AIC_SRCTYPE_RISING;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_LOW;
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else
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return -EINVAL;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
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srctype = AT91_AIC_SRCTYPE_FALLING;
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else
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return -EINVAL;
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break;
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default:
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return -EINVAL;
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}
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smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
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at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
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return 0;
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}
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#ifdef CONFIG_PM
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static u32 wakeups;
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static u32 backups;
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static int at91_aic_set_wake(struct irq_data *d, unsigned value)
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{
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if (unlikely(d->hwirq >= NR_AIC_IRQS))
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return -EINVAL;
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if (value)
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wakeups |= (1 << d->hwirq);
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else
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wakeups &= ~(1 << d->hwirq);
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return 0;
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}
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void at91_irq_suspend(void)
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{
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backups = at91_aic_read(AT91_AIC_IMR);
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at91_aic_write(AT91_AIC_IDCR, backups);
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at91_aic_write(AT91_AIC_IECR, wakeups);
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}
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void at91_irq_resume(void)
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{
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at91_aic_write(AT91_AIC_IDCR, wakeups);
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at91_aic_write(AT91_AIC_IECR, backups);
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}
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#else
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#define at91_aic_set_wake NULL
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#endif
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static struct irq_chip at91_aic_chip = {
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.name = "AIC",
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.irq_ack = at91_aic_mask_irq,
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.irq_mask = at91_aic_mask_irq,
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.irq_unmask = at91_aic_unmask_irq,
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.irq_set_type = at91_aic_set_type,
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.irq_set_wake = at91_aic_set_wake,
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};
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static void __init at91_aic_hw_init(unsigned int spu_vector)
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{
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int i;
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/*
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* Perform 8 End Of Interrupt Command to make sure AIC
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* will not Lock out nIRQ
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*/
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for (i = 0; i < 8; i++)
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at91_aic_write(AT91_AIC_EOICR, 0);
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/*
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* Spurious Interrupt ID in Spurious Vector Register.
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* When there is no current interrupt, the IRQ Vector Register
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* reads the value stored in AIC_SPU
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*/
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at91_aic_write(AT91_AIC_SPU, spu_vector);
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/* No debugging in AIC: Debug (Protect) Control Register */
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at91_aic_write(AT91_AIC_DCR, 0);
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/* Disable and clear all interrupts initially */
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at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
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at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
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}
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#if defined(CONFIG_OF)
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static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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/* Put virq number in Source Vector Register */
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at91_aic_write(AT91_AIC_SVR(hw), virq);
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/* Active Low interrupt, without priority */
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at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);
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irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops at91_aic_irq_ops = {
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.map = at91_aic_irq_map,
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.xlate = irq_domain_xlate_twocell,
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};
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int __init at91_aic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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at91_aic_base = of_iomap(node, 0);
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at91_aic_np = node;
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at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS,
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&at91_aic_irq_ops, NULL);
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if (!at91_aic_domain)
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panic("Unable to add AIC irq domain (DT)\n");
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irq_set_default_host(at91_aic_domain);
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at91_aic_hw_init(NR_AIC_IRQS);
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return 0;
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}
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#endif
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/*
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* Initialize the AIC interrupt controller.
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*/
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void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
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{
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unsigned int i;
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int irq_base;
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at91_aic_base = ioremap(AT91_AIC, 512);
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if (!at91_aic_base)
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panic("Unable to ioremap AIC registers\n");
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/* Add irq domain for AIC */
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irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0);
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if (irq_base < 0) {
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WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
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irq_base = 0;
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}
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at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS,
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irq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (!at91_aic_domain)
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panic("Unable to add AIC irq domain\n");
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irq_set_default_host(at91_aic_domain);
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/*
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* The IVR is used by macro get_irqnr_and_base to read and verify.
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* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
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*/
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for (i = 0; i < NR_AIC_IRQS; i++) {
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/* Put hardware irq number in Source Vector Register: */
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at91_aic_write(AT91_AIC_SVR(i), i);
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/* Active Low interrupt, with the specified priority */
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at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
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irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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at91_aic_hw_init(NR_AIC_IRQS);
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}
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