424 lines
11 KiB
C
424 lines
11 KiB
C
/*
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* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
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* (C) 2005 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
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*
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* First cut with LBA48/ATAPI
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*
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* TODO:
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* Channel interlock/reset on both required ?
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_pdc202xx_old"
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#define DRV_VERSION "0.2.1"
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/**
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* pdc2024x_pre_reset - probe begin
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* @ap: ATA port
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*
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* Set up cable type and use generic probe init
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*/
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static int pdc2024x_pre_reset(struct ata_port *ap)
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{
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ap->cbl = ATA_CBL_PATA40;
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return ata_std_prereset(ap);
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}
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static void pdc2024x_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, pdc2024x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
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}
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static int pdc2026x_pre_reset(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u16 cis;
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pci_read_config_word(pdev, 0x50, &cis);
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if (cis & (1 << (10 + ap->port_no)))
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ap->cbl = ATA_CBL_PATA80;
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else
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ap->cbl = ATA_CBL_PATA40;
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return ata_std_prereset(ap);
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}
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static void pdc2026x_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, pdc2026x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
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}
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/**
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* pdc_configure_piomode - set chip PIO timing
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* @ap: ATA interface
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* @adev: ATA device
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* @pio: PIO mode
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* so a configure_dmamode call will undo any work we do here and vice
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* versa
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*/
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static void pdc_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int port = 0x60 + 4 * ap->port_no + 2 * adev->devno;
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static u16 pio_timing[5] = {
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0x0913, 0x050C , 0x0308, 0x0206, 0x0104
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};
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u8 r_ap, r_bp;
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pci_read_config_byte(pdev, port, &r_ap);
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pci_read_config_byte(pdev, port + 1, &r_bp);
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r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
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r_bp &= ~0x07;
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r_ap |= (pio_timing[pio] >> 8);
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r_bp |= (pio_timing[pio] & 0xFF);
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if (ata_pio_need_iordy(adev))
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r_ap |= 0x20; /* IORDY enable */
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if (adev->class == ATA_DEV_ATA)
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r_ap |= 0x10; /* FIFO enable */
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pci_write_config_byte(pdev, port, r_ap);
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pci_write_config_byte(pdev, port + 1, r_bp);
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}
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/**
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* pdc_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* but we want to set the PIO timing by default.
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*/
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static void pdc_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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pdc_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
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}
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/**
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* pdc_configure_dmamode - set DMA mode in chip
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Load DMA cycle times into the chip ready for a DMA transfer
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* to occur.
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*/
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static void pdc_set_dmamode(struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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int port = 0x60 + 4 * ap->port_no + 2 * adev->devno;
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static u8 udma_timing[6][2] = {
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{ 0x60, 0x03 }, /* 33 Mhz Clock */
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{ 0x40, 0x02 },
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{ 0x20, 0x01 },
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{ 0x40, 0x02 }, /* 66 Mhz Clock */
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{ 0x20, 0x01 },
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{ 0x20, 0x01 }
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};
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u8 r_bp, r_cp;
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pci_read_config_byte(pdev, port + 1, &r_bp);
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pci_read_config_byte(pdev, port + 2, &r_cp);
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r_bp &= ~0xF0;
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r_cp &= ~0x0F;
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if (adev->dma_mode >= XFER_UDMA_0) {
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int speed = adev->dma_mode - XFER_UDMA_0;
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r_bp |= udma_timing[speed][0];
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r_cp |= udma_timing[speed][1];
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} else {
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int speed = adev->dma_mode - XFER_MW_DMA_0;
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r_bp |= 0x60;
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r_cp |= (5 - speed);
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}
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pci_write_config_byte(pdev, port + 1, r_bp);
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pci_write_config_byte(pdev, port + 2, r_cp);
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}
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/**
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* pdc2026x_bmdma_start - DMA engine begin
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* @qc: ATA command
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*
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* In UDMA3 or higher we have to clock switch for the duration of the
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* DMA transfer sequence.
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*/
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static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct ata_taskfile *tf = &qc->tf;
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int sel66 = ap->port_no ? 0x08: 0x02;
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unsigned long master = ap->host->ports[0]->ioaddr.bmdma_addr;
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unsigned long clock = master + 0x11;
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unsigned long atapi_reg = master + 0x20 + (4 * ap->port_no);
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u32 len;
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/* Check we keep host level locking here */
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if (adev->dma_mode >= XFER_UDMA_2)
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outb(inb(clock) | sel66, clock);
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else
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outb(inb(clock) & ~sel66, clock);
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/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
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and move to qc_issue ? */
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pdc_set_dmamode(ap, qc->dev);
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/* Cases the state machine will not complete correctly without help */
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if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATA_PROT_ATAPI_DMA)
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{
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if (tf->flags & ATA_TFLAG_LBA48)
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len = qc->nsect * 512;
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else
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len = qc->nbytes;
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if (tf->flags & ATA_TFLAG_WRITE)
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len |= 0x06000000;
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else
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len |= 0x05000000;
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outl(len, atapi_reg);
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}
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/* Activate DMA */
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ata_bmdma_start(qc);
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}
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/**
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* pdc2026x_bmdma_end - DMA engine stop
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* @qc: ATA command
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*
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* After a DMA completes we need to put the clock back to 33MHz for
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* PIO timings.
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*/
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static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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struct ata_taskfile *tf = &qc->tf;
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int sel66 = ap->port_no ? 0x08: 0x02;
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/* The clock bits are in the same register for both channels */
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unsigned long master = ap->host->ports[0]->ioaddr.bmdma_addr;
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unsigned long clock = master + 0x11;
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unsigned long atapi_reg = master + 0x20 + (4 * ap->port_no);
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/* Cases the state machine will not complete correctly */
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if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) {
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outl(0, atapi_reg);
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outb(inb(clock) & ~sel66, clock);
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}
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/* Check we keep host level locking here */
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/* Flip back to 33Mhz for PIO */
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if (adev->dma_mode >= XFER_UDMA_2)
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outb(inb(clock) & ~sel66, clock);
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ata_bmdma_stop(qc);
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}
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/**
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* pdc2026x_dev_config - device setup hook
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* @ap: ATA port
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* @adev: newly found device
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*
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* Perform chip specific early setup. We need to lock the transfer
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* sizes to 8bit to avoid making the state engine on the 2026x cards
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* barf.
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*/
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static void pdc2026x_dev_config(struct ata_port *ap, struct ata_device *adev)
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{
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adev->max_sectors = 256;
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}
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static struct scsi_host_template pdc_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.max_sectors = ATA_MAX_SECTORS,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.bios_param = ata_std_bios_param,
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};
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static struct ata_port_operations pdc2024x_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = pdc_set_piomode,
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.set_dmamode = pdc_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = pdc2024x_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop
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};
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static struct ata_port_operations pdc2026x_port_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = pdc_set_piomode,
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.set_dmamode = pdc_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.dev_config = pdc2026x_dev_config,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = pdc2026x_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = pdc2026x_bmdma_start,
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.bmdma_stop = pdc2026x_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_pio_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.port_start = ata_port_start,
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.port_stop = ata_port_stop,
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.host_stop = ata_host_stop
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};
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static int pdc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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static struct ata_port_info info[3] = {
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{
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.sht = &pdc_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA2,
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.port_ops = &pdc2024x_port_ops
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},
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{
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.sht = &pdc_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA4,
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.port_ops = &pdc2026x_port_ops
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},
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{
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.sht = &pdc_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x07,
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.udma_mask = ATA_UDMA5,
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.port_ops = &pdc2026x_port_ops
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}
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};
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static struct ata_port_info *port_info[2];
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port_info[0] = port_info[1] = &info[id->driver_data];
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if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
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struct pci_dev *bridge = dev->bus->self;
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/* Don't grab anything behind a Promise I2O RAID */
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if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
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if( bridge->device == PCI_DEVICE_ID_INTEL_I960)
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return -ENODEV;
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if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
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return -ENODEV;
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}
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}
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return ata_pci_init_one(dev, port_info, 2);
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}
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static struct pci_device_id pdc[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0},
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{ PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1},
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{ PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1},
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{ PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2},
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{ PCI_DEVICE(PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2},
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{ 0, },
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};
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static struct pci_driver pdc_pci_driver = {
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.name = DRV_NAME,
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.id_table = pdc,
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.probe = pdc_init_one,
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.remove = ata_pci_remove_one
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};
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static int __init pdc_init(void)
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{
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return pci_register_driver(&pdc_pci_driver);
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}
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static void __exit pdc_exit(void)
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{
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pci_unregister_driver(&pdc_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, pdc);
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MODULE_VERSION(DRV_VERSION);
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module_init(pdc_init);
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module_exit(pdc_exit);
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