895 lines
25 KiB
C
895 lines
25 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Broadcom
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*/
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#include <linux/delay.h>
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#include <linux/refcount.h>
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#include <linux/uaccess.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_debugfs.h>
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#include <drm/drm_device.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_mm.h>
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#include <drm/drm_modeset_lock.h>
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#include "uapi/drm/vc4_drm.h"
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struct drm_device;
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struct drm_gem_object;
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/* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
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* this.
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*/
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enum vc4_kernel_bo_type {
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/* Any kernel allocation (gem_create_object hook) before it
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* gets another type set.
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*/
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VC4_BO_TYPE_KERNEL,
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VC4_BO_TYPE_V3D,
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VC4_BO_TYPE_V3D_SHADER,
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VC4_BO_TYPE_DUMB,
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VC4_BO_TYPE_BIN,
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VC4_BO_TYPE_RCL,
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VC4_BO_TYPE_BCL,
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VC4_BO_TYPE_KERNEL_CACHE,
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VC4_BO_TYPE_COUNT
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};
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/* Performance monitor object. The perform lifetime is controlled by userspace
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* using perfmon related ioctls. A perfmon can be attached to a submit_cl
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* request, and when this is the case, HW perf counters will be activated just
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* before the submit_cl is submitted to the GPU and disabled when the job is
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* done. This way, only events related to a specific job will be counted.
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*/
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struct vc4_perfmon {
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/* Tracks the number of users of the perfmon, when this counter reaches
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* zero the perfmon is destroyed.
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*/
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refcount_t refcnt;
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/* Number of counters activated in this perfmon instance
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* (should be less than DRM_VC4_MAX_PERF_COUNTERS).
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*/
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u8 ncounters;
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/* Events counted by the HW perf counters. */
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u8 events[DRM_VC4_MAX_PERF_COUNTERS];
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/* Storage for counter values. Counters are incremented by the HW
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* perf counter values every time the perfmon is attached to a GPU job.
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* This way, perfmon users don't have to retrieve the results after
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* each job if they want to track events covering several submissions.
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* Note that counter values can't be reset, but you can fake a reset by
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* destroying the perfmon and creating a new one.
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*/
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u64 counters[0];
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};
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struct vc4_dev {
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struct drm_device *dev;
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struct vc4_hdmi *hdmi;
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struct vc4_hvs *hvs;
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struct vc4_v3d *v3d;
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struct vc4_dpi *dpi;
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struct vc4_dsi *dsi1;
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struct vc4_vec *vec;
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struct vc4_txp *txp;
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struct vc4_hang_state *hang_state;
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/* The kernel-space BO cache. Tracks buffers that have been
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* unreferenced by all other users (refcounts of 0!) but not
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* yet freed, so we can do cheap allocations.
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*/
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struct vc4_bo_cache {
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/* Array of list heads for entries in the BO cache,
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* based on number of pages, so we can do O(1) lookups
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* in the cache when allocating.
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*/
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struct list_head *size_list;
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uint32_t size_list_size;
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/* List of all BOs in the cache, ordered by age, so we
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* can do O(1) lookups when trying to free old
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* buffers.
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*/
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struct list_head time_list;
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struct work_struct time_work;
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struct timer_list time_timer;
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} bo_cache;
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u32 num_labels;
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struct vc4_label {
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const char *name;
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u32 num_allocated;
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u32 size_allocated;
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} *bo_labels;
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/* Protects bo_cache and bo_labels. */
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struct mutex bo_lock;
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/* Purgeable BO pool. All BOs in this pool can have their memory
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* reclaimed if the driver is unable to allocate new BOs. We also
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* keep stats related to the purge mechanism here.
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*/
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struct {
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struct list_head list;
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unsigned int num;
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size_t size;
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unsigned int purged_num;
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size_t purged_size;
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struct mutex lock;
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} purgeable;
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uint64_t dma_fence_context;
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/* Sequence number for the last job queued in bin_job_list.
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* Starts at 0 (no jobs emitted).
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*/
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uint64_t emit_seqno;
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/* Sequence number for the last completed job on the GPU.
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* Starts at 0 (no jobs completed).
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*/
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uint64_t finished_seqno;
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/* List of all struct vc4_exec_info for jobs to be executed in
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* the binner. The first job in the list is the one currently
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* programmed into ct0ca for execution.
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*/
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struct list_head bin_job_list;
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/* List of all struct vc4_exec_info for jobs that have
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* completed binning and are ready for rendering. The first
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* job in the list is the one currently programmed into ct1ca
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* for execution.
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*/
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struct list_head render_job_list;
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/* List of the finished vc4_exec_infos waiting to be freed by
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* job_done_work.
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*/
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struct list_head job_done_list;
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/* Spinlock used to synchronize the job_list and seqno
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* accesses between the IRQ handler and GEM ioctls.
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*/
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spinlock_t job_lock;
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wait_queue_head_t job_wait_queue;
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struct work_struct job_done_work;
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/* Used to track the active perfmon if any. Access to this field is
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* protected by job_lock.
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*/
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struct vc4_perfmon *active_perfmon;
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/* List of struct vc4_seqno_cb for callbacks to be made from a
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* workqueue when the given seqno is passed.
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*/
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struct list_head seqno_cb_list;
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/* The memory used for storing binner tile alloc, tile state,
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* and overflow memory allocations. This is freed when V3D
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* powers down.
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*/
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struct vc4_bo *bin_bo;
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/* Size of blocks allocated within bin_bo. */
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uint32_t bin_alloc_size;
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/* Bitmask of the bin_alloc_size chunks in bin_bo that are
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* used.
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*/
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uint32_t bin_alloc_used;
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/* Bitmask of the current bin_alloc used for overflow memory. */
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uint32_t bin_alloc_overflow;
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/* Incremented when an underrun error happened after an atomic commit.
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* This is particularly useful to detect when a specific modeset is too
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* demanding in term of memory or HVS bandwidth which is hard to guess
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* at atomic check time.
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*/
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atomic_t underrun;
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struct work_struct overflow_mem_work;
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int power_refcount;
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/* Set to true when the load tracker is active. */
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bool load_tracker_enabled;
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/* Mutex controlling the power refcount. */
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struct mutex power_lock;
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struct {
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struct timer_list timer;
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struct work_struct reset_work;
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} hangcheck;
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struct semaphore async_modeset;
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struct drm_modeset_lock ctm_state_lock;
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struct drm_private_obj ctm_manager;
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struct drm_private_obj load_tracker;
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/* List of vc4_debugfs_info_entry for adding to debugfs once
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* the minor is available (after drm_dev_register()).
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*/
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struct list_head debugfs_list;
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/* Mutex for binner bo allocation. */
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struct mutex bin_bo_lock;
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/* Reference count for our binner bo. */
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struct kref bin_bo_kref;
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};
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static inline struct vc4_dev *
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to_vc4_dev(struct drm_device *dev)
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{
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return (struct vc4_dev *)dev->dev_private;
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}
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struct vc4_bo {
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struct drm_gem_cma_object base;
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/* seqno of the last job to render using this BO. */
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uint64_t seqno;
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/* seqno of the last job to use the RCL to write to this BO.
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*
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* Note that this doesn't include binner overflow memory
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* writes.
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*/
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uint64_t write_seqno;
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bool t_format;
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/* List entry for the BO's position in either
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* vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
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*/
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struct list_head unref_head;
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/* Time in jiffies when the BO was put in vc4->bo_cache. */
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unsigned long free_time;
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/* List entry for the BO's position in vc4_dev->bo_cache.size_list */
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struct list_head size_head;
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/* Struct for shader validation state, if created by
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* DRM_IOCTL_VC4_CREATE_SHADER_BO.
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*/
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struct vc4_validated_shader_info *validated_shader;
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/* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
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* for user-allocated labels.
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*/
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int label;
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/* Count the number of active users. This is needed to determine
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* whether we can move the BO to the purgeable list or not (when the BO
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* is used by the GPU or the display engine we can't purge it).
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*/
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refcount_t usecnt;
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/* Store purgeable/purged state here */
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u32 madv;
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struct mutex madv_lock;
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};
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static inline struct vc4_bo *
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to_vc4_bo(struct drm_gem_object *bo)
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{
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return (struct vc4_bo *)bo;
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}
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struct vc4_fence {
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struct dma_fence base;
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struct drm_device *dev;
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/* vc4 seqno for signaled() test */
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uint64_t seqno;
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};
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static inline struct vc4_fence *
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to_vc4_fence(struct dma_fence *fence)
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{
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return (struct vc4_fence *)fence;
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}
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struct vc4_seqno_cb {
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struct work_struct work;
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uint64_t seqno;
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void (*func)(struct vc4_seqno_cb *cb);
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};
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struct vc4_v3d {
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struct vc4_dev *vc4;
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struct platform_device *pdev;
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void __iomem *regs;
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struct clk *clk;
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struct debugfs_regset32 regset;
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};
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struct vc4_hvs {
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struct platform_device *pdev;
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void __iomem *regs;
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u32 __iomem *dlist;
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/* Memory manager for CRTCs to allocate space in the display
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* list. Units are dwords.
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*/
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struct drm_mm dlist_mm;
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/* Memory manager for the LBM memory used by HVS scaling. */
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struct drm_mm lbm_mm;
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spinlock_t mm_lock;
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struct drm_mm_node mitchell_netravali_filter;
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struct debugfs_regset32 regset;
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};
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struct vc4_plane {
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struct drm_plane base;
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};
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static inline struct vc4_plane *
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to_vc4_plane(struct drm_plane *plane)
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{
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return (struct vc4_plane *)plane;
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}
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enum vc4_scaling_mode {
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VC4_SCALING_NONE,
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VC4_SCALING_TPZ,
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VC4_SCALING_PPF,
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};
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struct vc4_plane_state {
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struct drm_plane_state base;
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/* System memory copy of the display list for this element, computed
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* at atomic_check time.
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*/
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u32 *dlist;
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u32 dlist_size; /* Number of dwords allocated for the display list */
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u32 dlist_count; /* Number of used dwords in the display list. */
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/* Offset in the dlist to various words, for pageflip or
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* cursor updates.
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*/
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u32 pos0_offset;
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u32 pos2_offset;
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u32 ptr0_offset;
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u32 lbm_offset;
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/* Offset where the plane's dlist was last stored in the
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* hardware at vc4_crtc_atomic_flush() time.
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*/
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u32 __iomem *hw_dlist;
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/* Clipped coordinates of the plane on the display. */
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int crtc_x, crtc_y, crtc_w, crtc_h;
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/* Clipped area being scanned from in the FB. */
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u32 src_x, src_y;
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u32 src_w[2], src_h[2];
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/* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
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enum vc4_scaling_mode x_scaling[2], y_scaling[2];
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bool is_unity;
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bool is_yuv;
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/* Offset to start scanning out from the start of the plane's
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* BO.
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*/
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u32 offsets[3];
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/* Our allocation in LBM for temporary storage during scaling. */
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struct drm_mm_node lbm;
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/* Set when the plane has per-pixel alpha content or does not cover
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* the entire screen. This is a hint to the CRTC that it might need
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* to enable background color fill.
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*/
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bool needs_bg_fill;
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/* Mark the dlist as initialized. Useful to avoid initializing it twice
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* when async update is not possible.
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*/
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bool dlist_initialized;
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/* Load of this plane on the HVS block. The load is expressed in HVS
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* cycles/sec.
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*/
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u64 hvs_load;
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/* Memory bandwidth needed for this plane. This is expressed in
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* bytes/sec.
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*/
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u64 membus_load;
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};
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static inline struct vc4_plane_state *
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to_vc4_plane_state(struct drm_plane_state *state)
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{
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return (struct vc4_plane_state *)state;
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}
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enum vc4_encoder_type {
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VC4_ENCODER_TYPE_NONE,
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VC4_ENCODER_TYPE_HDMI,
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VC4_ENCODER_TYPE_VEC,
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VC4_ENCODER_TYPE_DSI0,
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VC4_ENCODER_TYPE_DSI1,
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VC4_ENCODER_TYPE_SMI,
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VC4_ENCODER_TYPE_DPI,
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};
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struct vc4_encoder {
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struct drm_encoder base;
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enum vc4_encoder_type type;
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u32 clock_select;
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};
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static inline struct vc4_encoder *
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to_vc4_encoder(struct drm_encoder *encoder)
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{
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return container_of(encoder, struct vc4_encoder, base);
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}
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struct vc4_crtc_data {
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/* Which channel of the HVS this pixelvalve sources from. */
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int hvs_channel;
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enum vc4_encoder_type encoder_types[4];
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const char *debugfs_name;
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};
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struct vc4_crtc {
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struct drm_crtc base;
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struct platform_device *pdev;
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const struct vc4_crtc_data *data;
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void __iomem *regs;
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/* Timestamp at start of vblank irq - unaffected by lock delays. */
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ktime_t t_vblank;
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/* Which HVS channel we're using for our CRTC. */
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int channel;
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u8 lut_r[256];
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u8 lut_g[256];
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u8 lut_b[256];
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/* Size in pixels of the COB memory allocated to this CRTC. */
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u32 cob_size;
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struct drm_pending_vblank_event *event;
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struct debugfs_regset32 regset;
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};
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static inline struct vc4_crtc *
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to_vc4_crtc(struct drm_crtc *crtc)
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{
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return (struct vc4_crtc *)crtc;
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}
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#define V3D_READ(offset) readl(vc4->v3d->regs + offset)
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#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
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#define HVS_READ(offset) readl(vc4->hvs->regs + offset)
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#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
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#define VC4_REG32(reg) { .name = #reg, .offset = reg }
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struct vc4_exec_info {
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/* Sequence number for this bin/render job. */
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uint64_t seqno;
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/* Latest write_seqno of any BO that binning depends on. */
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uint64_t bin_dep_seqno;
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struct dma_fence *fence;
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/* Last current addresses the hardware was processing when the
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* hangcheck timer checked on us.
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*/
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uint32_t last_ct0ca, last_ct1ca;
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/* Kernel-space copy of the ioctl arguments */
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struct drm_vc4_submit_cl *args;
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/* This is the array of BOs that were looked up at the start of exec.
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* Command validation will use indices into this array.
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*/
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struct drm_gem_cma_object **bo;
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uint32_t bo_count;
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/* List of BOs that are being written by the RCL. Other than
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* the binner temporary storage, this is all the BOs written
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* by the job.
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*/
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struct drm_gem_cma_object *rcl_write_bo[4];
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uint32_t rcl_write_bo_count;
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/* Pointers for our position in vc4->job_list */
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struct list_head head;
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/* List of other BOs used in the job that need to be released
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* once the job is complete.
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*/
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struct list_head unref_list;
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/* Current unvalidated indices into @bo loaded by the non-hardware
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* VC4_PACKET_GEM_HANDLES.
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*/
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uint32_t bo_index[2];
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/* This is the BO where we store the validated command lists, shader
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* records, and uniforms.
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*/
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struct drm_gem_cma_object *exec_bo;
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/**
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* This tracks the per-shader-record state (packet 64) that
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* determines the length of the shader record and the offset
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* it's expected to be found at. It gets read in from the
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* command lists.
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*/
|
|
struct vc4_shader_state {
|
|
uint32_t addr;
|
|
/* Maximum vertex index referenced by any primitive using this
|
|
* shader state.
|
|
*/
|
|
uint32_t max_index;
|
|
} *shader_state;
|
|
|
|
/** How many shader states the user declared they were using. */
|
|
uint32_t shader_state_size;
|
|
/** How many shader state records the validator has seen. */
|
|
uint32_t shader_state_count;
|
|
|
|
bool found_tile_binning_mode_config_packet;
|
|
bool found_start_tile_binning_packet;
|
|
bool found_increment_semaphore_packet;
|
|
bool found_flush;
|
|
uint8_t bin_tiles_x, bin_tiles_y;
|
|
/* Physical address of the start of the tile alloc array
|
|
* (where each tile's binned CL will start)
|
|
*/
|
|
uint32_t tile_alloc_offset;
|
|
/* Bitmask of which binner slots are freed when this job completes. */
|
|
uint32_t bin_slots;
|
|
|
|
/**
|
|
* Computed addresses pointing into exec_bo where we start the
|
|
* bin thread (ct0) and render thread (ct1).
|
|
*/
|
|
uint32_t ct0ca, ct0ea;
|
|
uint32_t ct1ca, ct1ea;
|
|
|
|
/* Pointer to the unvalidated bin CL (if present). */
|
|
void *bin_u;
|
|
|
|
/* Pointers to the shader recs. These paddr gets incremented as CL
|
|
* packets are relocated in validate_gl_shader_state, and the vaddrs
|
|
* (u and v) get incremented and size decremented as the shader recs
|
|
* themselves are validated.
|
|
*/
|
|
void *shader_rec_u;
|
|
void *shader_rec_v;
|
|
uint32_t shader_rec_p;
|
|
uint32_t shader_rec_size;
|
|
|
|
/* Pointers to the uniform data. These pointers are incremented, and
|
|
* size decremented, as each batch of uniforms is uploaded.
|
|
*/
|
|
void *uniforms_u;
|
|
void *uniforms_v;
|
|
uint32_t uniforms_p;
|
|
uint32_t uniforms_size;
|
|
|
|
/* Pointer to a performance monitor object if the user requested it,
|
|
* NULL otherwise.
|
|
*/
|
|
struct vc4_perfmon *perfmon;
|
|
|
|
/* Whether the exec has taken a reference to the binner BO, which should
|
|
* happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet.
|
|
*/
|
|
bool bin_bo_used;
|
|
};
|
|
|
|
/* Per-open file private data. Any driver-specific resource that has to be
|
|
* released when the DRM file is closed should be placed here.
|
|
*/
|
|
struct vc4_file {
|
|
struct {
|
|
struct idr idr;
|
|
struct mutex lock;
|
|
} perfmon;
|
|
|
|
bool bin_bo_used;
|
|
};
|
|
|
|
static inline struct vc4_exec_info *
|
|
vc4_first_bin_job(struct vc4_dev *vc4)
|
|
{
|
|
return list_first_entry_or_null(&vc4->bin_job_list,
|
|
struct vc4_exec_info, head);
|
|
}
|
|
|
|
static inline struct vc4_exec_info *
|
|
vc4_first_render_job(struct vc4_dev *vc4)
|
|
{
|
|
return list_first_entry_or_null(&vc4->render_job_list,
|
|
struct vc4_exec_info, head);
|
|
}
|
|
|
|
static inline struct vc4_exec_info *
|
|
vc4_last_render_job(struct vc4_dev *vc4)
|
|
{
|
|
if (list_empty(&vc4->render_job_list))
|
|
return NULL;
|
|
return list_last_entry(&vc4->render_job_list,
|
|
struct vc4_exec_info, head);
|
|
}
|
|
|
|
/**
|
|
* struct vc4_texture_sample_info - saves the offsets into the UBO for texture
|
|
* setup parameters.
|
|
*
|
|
* This will be used at draw time to relocate the reference to the texture
|
|
* contents in p0, and validate that the offset combined with
|
|
* width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
|
|
* Note that the hardware treats unprovided config parameters as 0, so not all
|
|
* of them need to be set up for every texure sample, and we'll store ~0 as
|
|
* the offset to mark the unused ones.
|
|
*
|
|
* See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
|
|
* Setup") for definitions of the texture parameters.
|
|
*/
|
|
struct vc4_texture_sample_info {
|
|
bool is_direct;
|
|
uint32_t p_offset[4];
|
|
};
|
|
|
|
/**
|
|
* struct vc4_validated_shader_info - information about validated shaders that
|
|
* needs to be used from command list validation.
|
|
*
|
|
* For a given shader, each time a shader state record references it, we need
|
|
* to verify that the shader doesn't read more uniforms than the shader state
|
|
* record's uniform BO pointer can provide, and we need to apply relocations
|
|
* and validate the shader state record's uniforms that define the texture
|
|
* samples.
|
|
*/
|
|
struct vc4_validated_shader_info {
|
|
uint32_t uniforms_size;
|
|
uint32_t uniforms_src_size;
|
|
uint32_t num_texture_samples;
|
|
struct vc4_texture_sample_info *texture_samples;
|
|
|
|
uint32_t num_uniform_addr_offsets;
|
|
uint32_t *uniform_addr_offsets;
|
|
|
|
bool is_threaded;
|
|
};
|
|
|
|
/**
|
|
* _wait_for - magic (register) wait macro
|
|
*
|
|
* Does the right thing for modeset paths when run under kdgb or similar atomic
|
|
* contexts. Note that it's important that we check the condition again after
|
|
* having timed out, since the timeout could be due to preemption or similar and
|
|
* we've never had a chance to check the condition before the timeout.
|
|
*/
|
|
#define _wait_for(COND, MS, W) ({ \
|
|
unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
|
|
int ret__ = 0; \
|
|
while (!(COND)) { \
|
|
if (time_after(jiffies, timeout__)) { \
|
|
if (!(COND)) \
|
|
ret__ = -ETIMEDOUT; \
|
|
break; \
|
|
} \
|
|
if (W && drm_can_sleep()) { \
|
|
msleep(W); \
|
|
} else { \
|
|
cpu_relax(); \
|
|
} \
|
|
} \
|
|
ret__; \
|
|
})
|
|
|
|
#define wait_for(COND, MS) _wait_for(COND, MS, 1)
|
|
|
|
/* vc4_bo.c */
|
|
struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
|
|
void vc4_free_object(struct drm_gem_object *gem_obj);
|
|
struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
|
|
bool from_cache, enum vc4_kernel_bo_type type);
|
|
int vc4_dumb_create(struct drm_file *file_priv,
|
|
struct drm_device *dev,
|
|
struct drm_mode_create_dumb *args);
|
|
struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags);
|
|
int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
vm_fault_t vc4_fault(struct vm_fault *vmf);
|
|
int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
|
|
int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
|
|
struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
|
|
struct dma_buf_attachment *attach,
|
|
struct sg_table *sgt);
|
|
void *vc4_prime_vmap(struct drm_gem_object *obj);
|
|
int vc4_bo_cache_init(struct drm_device *dev);
|
|
void vc4_bo_cache_destroy(struct drm_device *dev);
|
|
int vc4_bo_inc_usecnt(struct vc4_bo *bo);
|
|
void vc4_bo_dec_usecnt(struct vc4_bo *bo);
|
|
void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
|
|
void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
|
|
|
|
/* vc4_crtc.c */
|
|
extern struct platform_driver vc4_crtc_driver;
|
|
bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
|
|
bool in_vblank_irq, int *vpos, int *hpos,
|
|
ktime_t *stime, ktime_t *etime,
|
|
const struct drm_display_mode *mode);
|
|
void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
|
|
void vc4_crtc_txp_armed(struct drm_crtc_state *state);
|
|
void vc4_crtc_get_margins(struct drm_crtc_state *state,
|
|
unsigned int *right, unsigned int *left,
|
|
unsigned int *top, unsigned int *bottom);
|
|
|
|
/* vc4_debugfs.c */
|
|
int vc4_debugfs_init(struct drm_minor *minor);
|
|
#ifdef CONFIG_DEBUG_FS
|
|
void vc4_debugfs_add_file(struct drm_device *drm,
|
|
const char *filename,
|
|
int (*show)(struct seq_file*, void*),
|
|
void *data);
|
|
void vc4_debugfs_add_regset32(struct drm_device *drm,
|
|
const char *filename,
|
|
struct debugfs_regset32 *regset);
|
|
#else
|
|
static inline void vc4_debugfs_add_file(struct drm_device *drm,
|
|
const char *filename,
|
|
int (*show)(struct seq_file*, void*),
|
|
void *data)
|
|
{
|
|
}
|
|
|
|
static inline void vc4_debugfs_add_regset32(struct drm_device *drm,
|
|
const char *filename,
|
|
struct debugfs_regset32 *regset)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
/* vc4_drv.c */
|
|
void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
|
|
|
|
/* vc4_dpi.c */
|
|
extern struct platform_driver vc4_dpi_driver;
|
|
|
|
/* vc4_dsi.c */
|
|
extern struct platform_driver vc4_dsi_driver;
|
|
|
|
/* vc4_fence.c */
|
|
extern const struct dma_fence_ops vc4_fence_ops;
|
|
|
|
/* vc4_gem.c */
|
|
void vc4_gem_init(struct drm_device *dev);
|
|
void vc4_gem_destroy(struct drm_device *dev);
|
|
int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
void vc4_submit_next_bin_job(struct drm_device *dev);
|
|
void vc4_submit_next_render_job(struct drm_device *dev);
|
|
void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
|
|
int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
|
|
uint64_t timeout_ns, bool interruptible);
|
|
void vc4_job_handle_completed(struct vc4_dev *vc4);
|
|
int vc4_queue_seqno_cb(struct drm_device *dev,
|
|
struct vc4_seqno_cb *cb, uint64_t seqno,
|
|
void (*func)(struct vc4_seqno_cb *cb));
|
|
int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
|
|
/* vc4_hdmi.c */
|
|
extern struct platform_driver vc4_hdmi_driver;
|
|
|
|
/* vc4_vec.c */
|
|
extern struct platform_driver vc4_vec_driver;
|
|
|
|
/* vc4_txp.c */
|
|
extern struct platform_driver vc4_txp_driver;
|
|
|
|
/* vc4_irq.c */
|
|
irqreturn_t vc4_irq(int irq, void *arg);
|
|
void vc4_irq_preinstall(struct drm_device *dev);
|
|
int vc4_irq_postinstall(struct drm_device *dev);
|
|
void vc4_irq_uninstall(struct drm_device *dev);
|
|
void vc4_irq_reset(struct drm_device *dev);
|
|
|
|
/* vc4_hvs.c */
|
|
extern struct platform_driver vc4_hvs_driver;
|
|
void vc4_hvs_dump_state(struct drm_device *dev);
|
|
void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
|
|
void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
|
|
|
|
/* vc4_kms.c */
|
|
int vc4_kms_load(struct drm_device *dev);
|
|
|
|
/* vc4_plane.c */
|
|
struct drm_plane *vc4_plane_init(struct drm_device *dev,
|
|
enum drm_plane_type type);
|
|
u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
|
|
u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
|
|
void vc4_plane_async_set_fb(struct drm_plane *plane,
|
|
struct drm_framebuffer *fb);
|
|
|
|
/* vc4_v3d.c */
|
|
extern struct platform_driver vc4_v3d_driver;
|
|
extern const struct of_device_id vc4_v3d_dt_match[];
|
|
int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
|
|
int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used);
|
|
void vc4_v3d_bin_bo_put(struct vc4_dev *vc4);
|
|
int vc4_v3d_pm_get(struct vc4_dev *vc4);
|
|
void vc4_v3d_pm_put(struct vc4_dev *vc4);
|
|
|
|
/* vc4_validate.c */
|
|
int
|
|
vc4_validate_bin_cl(struct drm_device *dev,
|
|
void *validated,
|
|
void *unvalidated,
|
|
struct vc4_exec_info *exec);
|
|
|
|
int
|
|
vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
|
|
|
|
struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
|
|
uint32_t hindex);
|
|
|
|
int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
|
|
|
|
bool vc4_check_tex_size(struct vc4_exec_info *exec,
|
|
struct drm_gem_cma_object *fbo,
|
|
uint32_t offset, uint8_t tiling_format,
|
|
uint32_t width, uint32_t height, uint8_t cpp);
|
|
|
|
/* vc4_validate_shader.c */
|
|
struct vc4_validated_shader_info *
|
|
vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
|
|
|
|
/* vc4_perfmon.c */
|
|
void vc4_perfmon_get(struct vc4_perfmon *perfmon);
|
|
void vc4_perfmon_put(struct vc4_perfmon *perfmon);
|
|
void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
|
|
void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
|
|
bool capture);
|
|
struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
|
|
void vc4_perfmon_open_file(struct vc4_file *vc4file);
|
|
void vc4_perfmon_close_file(struct vc4_file *vc4file);
|
|
int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|
|
int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv);
|