344 lines
9.4 KiB
C
344 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2014 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#include <linux/binfmts.h>
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#include <linux/elf.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <asm/cpu-features.h>
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#include <asm/cpu-info.h>
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#ifdef CONFIG_MIPS_FP_SUPPORT
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/* Whether to accept legacy-NaN and 2008-NaN user binaries. */
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bool mips_use_nan_legacy;
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bool mips_use_nan_2008;
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/* FPU modes */
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enum {
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FP_FRE,
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FP_FR0,
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FP_FR1,
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};
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/**
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* struct mode_req - ABI FPU mode requirements
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* @single: The program being loaded needs an FPU but it will only issue
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* single precision instructions meaning that it can execute in
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* either FR0 or FR1.
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* @soft: The soft(-float) requirement means that the program being
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* loaded needs has no FPU dependency at all (i.e. it has no
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* FPU instructions).
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* @fr1: The program being loaded depends on FPU being in FR=1 mode.
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* @frdefault: The program being loaded depends on the default FPU mode.
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* That is FR0 for O32 and FR1 for N32/N64.
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* @fre: The program being loaded depends on FPU with FRE=1. This mode is
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* a bridge which uses FR=1 whilst still being able to maintain
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* full compatibility with pre-existing code using the O32 FP32
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* ABI.
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*
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* More information about the FP ABIs can be found here:
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*
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* https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#10.4.1._Basic_mode_set-up
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*
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*/
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struct mode_req {
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bool single;
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bool soft;
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bool fr1;
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bool frdefault;
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bool fre;
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};
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static const struct mode_req fpu_reqs[] = {
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[MIPS_ABI_FP_ANY] = { true, true, true, true, true },
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[MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true },
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[MIPS_ABI_FP_SINGLE] = { true, false, false, false, false },
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[MIPS_ABI_FP_SOFT] = { false, true, false, false, false },
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[MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
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[MIPS_ABI_FP_XX] = { false, false, true, true, true },
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[MIPS_ABI_FP_64] = { false, false, true, false, false },
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[MIPS_ABI_FP_64A] = { false, false, true, false, true }
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};
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/*
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* Mode requirements when .MIPS.abiflags is not present in the ELF.
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* Not present means that everything is acceptable except FR1.
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*/
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static struct mode_req none_req = { true, true, false, true, true };
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int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf,
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bool is_interp, struct arch_elf_state *state)
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{
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union {
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struct elf32_hdr e32;
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struct elf64_hdr e64;
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} *ehdr = _ehdr;
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struct elf32_phdr *phdr32 = _phdr;
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struct elf64_phdr *phdr64 = _phdr;
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struct mips_elf_abiflags_v0 abiflags;
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bool elf32;
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u32 flags;
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int ret;
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loff_t pos;
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elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
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flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
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/* Let's see if this is an O32 ELF */
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if (elf32) {
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if (flags & EF_MIPS_FP64) {
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/*
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* Set MIPS_ABI_FP_OLD_64 for EF_MIPS_FP64. We will override it
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* later if needed
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*/
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if (is_interp)
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state->interp_fp_abi = MIPS_ABI_FP_OLD_64;
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else
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state->fp_abi = MIPS_ABI_FP_OLD_64;
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}
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if (phdr32->p_type != PT_MIPS_ABIFLAGS)
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return 0;
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if (phdr32->p_filesz < sizeof(abiflags))
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return -EINVAL;
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pos = phdr32->p_offset;
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} else {
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if (phdr64->p_type != PT_MIPS_ABIFLAGS)
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return 0;
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if (phdr64->p_filesz < sizeof(abiflags))
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return -EINVAL;
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pos = phdr64->p_offset;
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}
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ret = kernel_read(elf, &abiflags, sizeof(abiflags), &pos);
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if (ret < 0)
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return ret;
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if (ret != sizeof(abiflags))
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return -EIO;
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/* Record the required FP ABIs for use by mips_check_elf */
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if (is_interp)
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state->interp_fp_abi = abiflags.fp_abi;
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else
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state->fp_abi = abiflags.fp_abi;
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return 0;
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}
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int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr,
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struct arch_elf_state *state)
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{
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union {
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struct elf32_hdr e32;
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struct elf64_hdr e64;
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} *ehdr = _ehdr;
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union {
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struct elf32_hdr e32;
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struct elf64_hdr e64;
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} *iehdr = _interp_ehdr;
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struct mode_req prog_req, interp_req;
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int fp_abi, interp_fp_abi, abi0, abi1, max_abi;
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bool elf32;
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u32 flags;
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elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
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flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags;
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/*
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* Determine the NaN personality, reject the binary if not allowed.
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* Also ensure that any interpreter matches the executable.
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*/
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if (flags & EF_MIPS_NAN2008) {
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if (mips_use_nan_2008)
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state->nan_2008 = 1;
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else
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return -ENOEXEC;
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} else {
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if (mips_use_nan_legacy)
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state->nan_2008 = 0;
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else
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return -ENOEXEC;
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}
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if (has_interpreter) {
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bool ielf32;
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u32 iflags;
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ielf32 = iehdr->e32.e_ident[EI_CLASS] == ELFCLASS32;
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iflags = ielf32 ? iehdr->e32.e_flags : iehdr->e64.e_flags;
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if ((flags ^ iflags) & EF_MIPS_NAN2008)
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return -ELIBBAD;
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}
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if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
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return 0;
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fp_abi = state->fp_abi;
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if (has_interpreter) {
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interp_fp_abi = state->interp_fp_abi;
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abi0 = min(fp_abi, interp_fp_abi);
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abi1 = max(fp_abi, interp_fp_abi);
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} else {
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abi0 = abi1 = fp_abi;
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}
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if (elf32 && !(flags & EF_MIPS_ABI2)) {
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/* Default to a mode capable of running code expecting FR=0 */
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state->overall_fp_mode = cpu_has_mips_r6 ? FP_FRE : FP_FR0;
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/* Allow all ABIs we know about */
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max_abi = MIPS_ABI_FP_64A;
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} else {
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/* MIPS64 code always uses FR=1, thus the default is easy */
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state->overall_fp_mode = FP_FR1;
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/* Disallow access to the various FPXX & FP64 ABIs */
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max_abi = MIPS_ABI_FP_SOFT;
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}
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if ((abi0 > max_abi && abi0 != MIPS_ABI_FP_UNKNOWN) ||
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(abi1 > max_abi && abi1 != MIPS_ABI_FP_UNKNOWN))
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return -ELIBBAD;
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/* It's time to determine the FPU mode requirements */
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prog_req = (abi0 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi0];
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interp_req = (abi1 == MIPS_ABI_FP_UNKNOWN) ? none_req : fpu_reqs[abi1];
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/*
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* Check whether the program's and interp's ABIs have a matching FPU
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* mode requirement.
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*/
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prog_req.single = interp_req.single && prog_req.single;
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prog_req.soft = interp_req.soft && prog_req.soft;
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prog_req.fr1 = interp_req.fr1 && prog_req.fr1;
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prog_req.frdefault = interp_req.frdefault && prog_req.frdefault;
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prog_req.fre = interp_req.fre && prog_req.fre;
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/*
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* Determine the desired FPU mode
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*
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* Decision making:
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*
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* - We want FR_FRE if FRE=1 and both FR=1 and FR=0 are false. This
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* means that we have a combination of program and interpreter
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* that inherently require the hybrid FP mode.
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* - If FR1 and FRDEFAULT is true, that means we hit the any-abi or
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* fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU
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* instructions so we don't care about the mode. We will simply use
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* the one preferred by the hardware. In fpxx case, that ABI can
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* handle both FR=1 and FR=0, so, again, we simply choose the one
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* preferred by the hardware. Next, if we only use single-precision
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* FPU instructions, and the default ABI FPU mode is not good
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* (ie single + any ABI combination), we set again the FPU mode to the
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* one is preferred by the hardware. Next, if we know that the code
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* will only use single-precision instructions, shown by single being
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* true but frdefault being false, then we again set the FPU mode to
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* the one that is preferred by the hardware.
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* - We want FP_FR1 if that's the only matching mode and the default one
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* is not good.
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* - Return with -ELIBADD if we can't find a matching FPU mode.
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*/
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if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1)
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state->overall_fp_mode = FP_FRE;
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else if ((prog_req.fr1 && prog_req.frdefault) ||
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(prog_req.single && !prog_req.frdefault))
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/* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */
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state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) &&
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cpu_has_mips_r2_r6) ?
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FP_FR1 : FP_FR0;
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else if (prog_req.fr1)
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state->overall_fp_mode = FP_FR1;
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else if (!prog_req.fre && !prog_req.frdefault &&
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!prog_req.fr1 && !prog_req.single && !prog_req.soft)
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return -ELIBBAD;
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return 0;
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}
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static inline void set_thread_fp_mode(int hybrid, int regs32)
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{
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if (hybrid)
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set_thread_flag(TIF_HYBRID_FPREGS);
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else
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clear_thread_flag(TIF_HYBRID_FPREGS);
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if (regs32)
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set_thread_flag(TIF_32BIT_FPREGS);
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else
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clear_thread_flag(TIF_32BIT_FPREGS);
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}
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void mips_set_personality_fp(struct arch_elf_state *state)
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{
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/*
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* This function is only ever called for O32 ELFs so we should
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* not be worried about N32/N64 binaries.
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*/
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if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
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return;
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switch (state->overall_fp_mode) {
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case FP_FRE:
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set_thread_fp_mode(1, 0);
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break;
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case FP_FR0:
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set_thread_fp_mode(0, 1);
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break;
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case FP_FR1:
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set_thread_fp_mode(0, 0);
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break;
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default:
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BUG();
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}
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}
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/*
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* Select the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
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* in FCSR according to the ELF NaN personality.
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*/
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void mips_set_personality_nan(struct arch_elf_state *state)
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{
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struct cpuinfo_mips *c = &boot_cpu_data;
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struct task_struct *t = current;
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t->thread.fpu.fcr31 = c->fpu_csr31;
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switch (state->nan_2008) {
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case 0:
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break;
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case 1:
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if (!(c->fpu_msk31 & FPU_CSR_NAN2008))
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t->thread.fpu.fcr31 |= FPU_CSR_NAN2008;
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if (!(c->fpu_msk31 & FPU_CSR_ABS2008))
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t->thread.fpu.fcr31 |= FPU_CSR_ABS2008;
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break;
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default:
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BUG();
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}
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}
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#endif /* CONFIG_MIPS_FP_SUPPORT */
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int mips_elf_read_implies_exec(void *elf_ex, int exstack)
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{
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if (exstack != EXSTACK_DISABLE_X) {
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/* The binary doesn't request a non-executable stack */
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return 1;
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}
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if (!cpu_has_rixi) {
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/* The CPU doesn't support non-executable memory */
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return 1;
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}
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return 0;
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}
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EXPORT_SYMBOL(mips_elf_read_implies_exec);
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