40 lines
1020 B
C
40 lines
1020 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Atom platform clocks for BayTrail and CherryTrail SoC.
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*
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* Copyright (C) 2016, Intel Corporation
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* Author: Irina Tirdea <irina.tirdea@intel.com>
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*/
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#ifndef __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
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#define __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
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/**
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* struct pmc_clk - PMC platform clock configuration
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*
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* @name: identified, typically pmc_plt_clk_<x>, x=[0..5]
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* @freq: in Hz, 19.2MHz and 25MHz (Baytrail only) supported
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* @parent_name: one of 'xtal' or 'osc'
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*/
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struct pmc_clk {
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const char *name;
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unsigned long freq;
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const char *parent_name;
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};
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/**
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* struct pmc_clk_data - common PMC clock configuration
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*
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* @base: PMC clock register base offset
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* @clks: pointer to set of registered clocks, typically 0..5
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* @critical: flag to indicate if firmware enabled pmc_plt_clks
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* should be marked as critial or not
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*/
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struct pmc_clk_data {
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void __iomem *base;
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const struct pmc_clk *clks;
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bool critical;
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};
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#endif /* __PLATFORM_DATA_X86_CLK_PMC_ATOM_H */
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