330 lines
8.7 KiB
C
330 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* DWC PCIe RC driver for Toshiba Visconti ARM SoC
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*
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* Copyright (C) 2021 Toshiba Electronic Device & Storage Corporation
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* Copyright (C) 2021 TOSHIBA CORPORATION
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*
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* Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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#include "../../pci.h"
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struct visconti_pcie {
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struct dw_pcie pci;
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void __iomem *ulreg_base;
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void __iomem *smu_base;
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void __iomem *mpu_base;
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struct clk *refclk;
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struct clk *coreclk;
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struct clk *auxclk;
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};
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#define PCIE_UL_REG_S_PCIE_MODE 0x00F4
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#define PCIE_UL_REG_S_PCIE_MODE_EP 0x00
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#define PCIE_UL_REG_S_PCIE_MODE_RC 0x04
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#define PCIE_UL_REG_S_PERSTN_CTRL 0x00F8
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#define PCIE_UL_IOM_PCIE_PERSTN_I_EN BIT(3)
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#define PCIE_UL_DIRECT_PERSTN_EN BIT(2)
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#define PCIE_UL_PERSTN_OUT BIT(1)
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#define PCIE_UL_DIRECT_PERSTN BIT(0)
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#define PCIE_UL_REG_S_PERSTN_CTRL_INIT (PCIE_UL_IOM_PCIE_PERSTN_I_EN | \
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PCIE_UL_DIRECT_PERSTN_EN | \
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PCIE_UL_DIRECT_PERSTN)
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#define PCIE_UL_REG_S_PHY_INIT_02 0x0104
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#define PCIE_UL_PHY0_SRAM_EXT_LD_DONE BIT(0)
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#define PCIE_UL_REG_S_PHY_INIT_03 0x0108
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#define PCIE_UL_PHY0_SRAM_INIT_DONE BIT(0)
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#define PCIE_UL_REG_S_INT_EVENT_MASK1 0x0138
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#define PCIE_UL_CFG_PME_INT BIT(0)
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#define PCIE_UL_CFG_LINK_EQ_REQ_INT BIT(1)
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#define PCIE_UL_EDMA_INT0 BIT(2)
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#define PCIE_UL_EDMA_INT1 BIT(3)
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#define PCIE_UL_EDMA_INT2 BIT(4)
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#define PCIE_UL_EDMA_INT3 BIT(5)
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#define PCIE_UL_S_INT_EVENT_MASK1_ALL (PCIE_UL_CFG_PME_INT | \
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PCIE_UL_CFG_LINK_EQ_REQ_INT | \
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PCIE_UL_EDMA_INT0 | \
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PCIE_UL_EDMA_INT1 | \
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PCIE_UL_EDMA_INT2 | \
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PCIE_UL_EDMA_INT3)
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#define PCIE_UL_REG_S_SB_MON 0x0198
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#define PCIE_UL_REG_S_SIG_MON 0x019C
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#define PCIE_UL_CORE_RST_N_MON BIT(0)
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#define PCIE_UL_REG_V_SII_DBG_00 0x0844
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#define PCIE_UL_REG_V_SII_GEN_CTRL_01 0x0860
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#define PCIE_UL_APP_LTSSM_ENABLE BIT(0)
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#define PCIE_UL_REG_V_PHY_ST_00 0x0864
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#define PCIE_UL_SMLH_LINK_UP BIT(0)
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#define PCIE_UL_REG_V_PHY_ST_02 0x0868
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#define PCIE_UL_S_DETECT_ACT 0x01
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#define PCIE_UL_S_L0 0x11
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#define PISMU_CKON_PCIE 0x0038
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#define PISMU_CKON_PCIE_AUX_CLK BIT(1)
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#define PISMU_CKON_PCIE_MSTR_ACLK BIT(0)
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#define PISMU_RSOFF_PCIE 0x0538
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#define PISMU_RSOFF_PCIE_ULREG_RST_N BIT(1)
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#define PISMU_RSOFF_PCIE_PWR_UP_RST_N BIT(0)
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#define PCIE_MPU_REG_MP_EN 0x0
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#define MPU_MP_EN_DISABLE BIT(0)
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/* Access registers in PCIe ulreg */
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static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg)
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{
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writel_relaxed(val, pcie->ulreg_base + reg);
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}
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static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg)
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{
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return readl_relaxed(pcie->ulreg_base + reg);
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}
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/* Access registers in PCIe smu */
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static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg)
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{
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writel_relaxed(val, pcie->smu_base + reg);
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}
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/* Access registers in PCIe mpu */
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static void visconti_mpu_writel(struct visconti_pcie *pcie, u32 val, u32 reg)
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{
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writel_relaxed(val, pcie->mpu_base + reg);
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}
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static u32 visconti_mpu_readl(struct visconti_pcie *pcie, u32 reg)
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{
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return readl_relaxed(pcie->mpu_base + reg);
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}
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static int visconti_pcie_link_up(struct dw_pcie *pci)
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{
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struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
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void __iomem *addr = pcie->ulreg_base;
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u32 val = readl_relaxed(addr + PCIE_UL_REG_V_PHY_ST_02);
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return !!(val & PCIE_UL_S_L0);
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}
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static int visconti_pcie_start_link(struct dw_pcie *pci)
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{
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struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
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void __iomem *addr = pcie->ulreg_base;
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u32 val;
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int ret;
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visconti_ulreg_writel(pcie, PCIE_UL_APP_LTSSM_ENABLE,
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PCIE_UL_REG_V_SII_GEN_CTRL_01);
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ret = readl_relaxed_poll_timeout(addr + PCIE_UL_REG_V_PHY_ST_02,
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val, (val & PCIE_UL_S_L0),
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90000, 100000);
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if (ret)
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return ret;
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visconti_ulreg_writel(pcie, PCIE_UL_S_INT_EVENT_MASK1_ALL,
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PCIE_UL_REG_S_INT_EVENT_MASK1);
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if (dw_pcie_link_up(pci)) {
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val = visconti_mpu_readl(pcie, PCIE_MPU_REG_MP_EN);
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visconti_mpu_writel(pcie, val & ~MPU_MP_EN_DISABLE,
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PCIE_MPU_REG_MP_EN);
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}
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return 0;
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}
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static void visconti_pcie_stop_link(struct dw_pcie *pci)
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{
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struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
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u32 val;
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val = visconti_ulreg_readl(pcie, PCIE_UL_REG_V_SII_GEN_CTRL_01);
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val &= ~PCIE_UL_APP_LTSSM_ENABLE;
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visconti_ulreg_writel(pcie, val, PCIE_UL_REG_V_SII_GEN_CTRL_01);
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val = visconti_mpu_readl(pcie, PCIE_MPU_REG_MP_EN);
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visconti_mpu_writel(pcie, val | MPU_MP_EN_DISABLE, PCIE_MPU_REG_MP_EN);
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}
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/*
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* In this SoC specification, the CPU bus outputs the offset value from
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* 0x40000000 to the PCIe bus, so 0x40000000 is subtracted from the CPU
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* bus address. This 0x40000000 is also based on io_base from DT.
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*/
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static u64 visconti_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 cpu_addr)
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{
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struct pcie_port *pp = &pci->pp;
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return cpu_addr & ~pp->io_base;
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.cpu_addr_fixup = visconti_pcie_cpu_addr_fixup,
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.link_up = visconti_pcie_link_up,
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.start_link = visconti_pcie_start_link,
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.stop_link = visconti_pcie_stop_link,
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};
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static int visconti_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
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void __iomem *addr;
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int err;
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u32 val;
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visconti_smu_writel(pcie,
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PISMU_CKON_PCIE_AUX_CLK | PISMU_CKON_PCIE_MSTR_ACLK,
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PISMU_CKON_PCIE);
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ndelay(250);
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visconti_smu_writel(pcie, PISMU_RSOFF_PCIE_ULREG_RST_N,
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PISMU_RSOFF_PCIE);
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visconti_ulreg_writel(pcie, PCIE_UL_REG_S_PCIE_MODE_RC,
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PCIE_UL_REG_S_PCIE_MODE);
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val = PCIE_UL_REG_S_PERSTN_CTRL_INIT;
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visconti_ulreg_writel(pcie, val, PCIE_UL_REG_S_PERSTN_CTRL);
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udelay(100);
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val |= PCIE_UL_PERSTN_OUT;
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visconti_ulreg_writel(pcie, val, PCIE_UL_REG_S_PERSTN_CTRL);
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udelay(100);
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visconti_smu_writel(pcie, PISMU_RSOFF_PCIE_PWR_UP_RST_N,
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PISMU_RSOFF_PCIE);
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addr = pcie->ulreg_base + PCIE_UL_REG_S_PHY_INIT_03;
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err = readl_relaxed_poll_timeout(addr, val,
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(val & PCIE_UL_PHY0_SRAM_INIT_DONE),
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100, 1000);
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if (err)
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return err;
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visconti_ulreg_writel(pcie, PCIE_UL_PHY0_SRAM_EXT_LD_DONE,
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PCIE_UL_REG_S_PHY_INIT_02);
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addr = pcie->ulreg_base + PCIE_UL_REG_S_SIG_MON;
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return readl_relaxed_poll_timeout(addr, val,
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(val & PCIE_UL_CORE_RST_N_MON), 100,
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1000);
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}
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static const struct dw_pcie_host_ops visconti_pcie_host_ops = {
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.host_init = visconti_pcie_host_init,
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};
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static int visconti_get_resources(struct platform_device *pdev,
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struct visconti_pcie *pcie)
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{
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struct device *dev = &pdev->dev;
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pcie->ulreg_base = devm_platform_ioremap_resource_byname(pdev, "ulreg");
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if (IS_ERR(pcie->ulreg_base))
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return PTR_ERR(pcie->ulreg_base);
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pcie->smu_base = devm_platform_ioremap_resource_byname(pdev, "smu");
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if (IS_ERR(pcie->smu_base))
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return PTR_ERR(pcie->smu_base);
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pcie->mpu_base = devm_platform_ioremap_resource_byname(pdev, "mpu");
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if (IS_ERR(pcie->mpu_base))
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return PTR_ERR(pcie->mpu_base);
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pcie->refclk = devm_clk_get(dev, "ref");
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if (IS_ERR(pcie->refclk))
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return dev_err_probe(dev, PTR_ERR(pcie->refclk),
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"Failed to get ref clock\n");
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pcie->coreclk = devm_clk_get(dev, "core");
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if (IS_ERR(pcie->coreclk))
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return dev_err_probe(dev, PTR_ERR(pcie->coreclk),
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"Failed to get core clock\n");
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pcie->auxclk = devm_clk_get(dev, "aux");
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if (IS_ERR(pcie->auxclk))
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return dev_err_probe(dev, PTR_ERR(pcie->auxclk),
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"Failed to get aux clock\n");
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return 0;
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}
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static int visconti_add_pcie_port(struct visconti_pcie *pcie,
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struct platform_device *pdev)
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{
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struct dw_pcie *pci = &pcie->pci;
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struct pcie_port *pp = &pci->pp;
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pp->irq = platform_get_irq_byname(pdev, "intr");
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if (pp->irq < 0)
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return pp->irq;
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pp->ops = &visconti_pcie_host_ops;
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return dw_pcie_host_init(pp);
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}
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static int visconti_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct visconti_pcie *pcie;
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struct dw_pcie *pci;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pci = &pcie->pci;
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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ret = visconti_get_resources(pdev, pcie);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, pcie);
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return visconti_add_pcie_port(pcie, pdev);
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}
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static const struct of_device_id visconti_pcie_match[] = {
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{ .compatible = "toshiba,visconti-pcie" },
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{},
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};
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static struct platform_driver visconti_pcie_driver = {
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.probe = visconti_pcie_probe,
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.driver = {
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.name = "visconti-pcie",
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.of_match_table = visconti_pcie_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(visconti_pcie_driver);
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