92 lines
2.3 KiB
C
92 lines
2.3 KiB
C
/*
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* arch/arm/mach-kirkwood/addr-map.c
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*
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* Address map functions for Marvell Kirkwood SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <plat/addr-map.h>
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#include "common.h"
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DEV_BUS 1
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#define TARGET_SRAM 3
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#define TARGET_PCIE 4
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#define ATTR_DEV_SPI_ROM 0x1e
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#define ATTR_DEV_BOOT 0x1d
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#define ATTR_DEV_NAND 0x2f
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#define ATTR_DEV_CS3 0x37
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#define ATTR_DEV_CS2 0x3b
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#define ATTR_DEV_CS1 0x3d
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#define ATTR_DEV_CS0 0x3e
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#define ATTR_PCIE_IO 0xe0
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#define ATTR_PCIE_MEM 0xe8
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#define ATTR_PCIE1_IO 0xd0
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#define ATTR_PCIE1_MEM 0xd8
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#define ATTR_SRAM 0x01
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/*
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* Description of the windows needed by the platform code
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*/
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static struct __initdata orion_addr_map_cfg addr_map_cfg = {
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.num_wins = 8,
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.remappable_wins = 4,
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.bridge_virt_base = BRIDGE_VIRT_BASE,
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};
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static const struct __initdata orion_addr_map_info addr_map_info[] = {
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/*
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* Windows for PCIe IO+MEM space.
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*/
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{ 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
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TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
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},
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{ 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
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TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
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},
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{ 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
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TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
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},
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{ 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
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TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
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},
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/*
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* Window for NAND controller.
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*/
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{ 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
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TARGET_DEV_BUS, ATTR_DEV_NAND, -1
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},
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/*
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* Window for SRAM.
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*/
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{ 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
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TARGET_SRAM, ATTR_SRAM, -1
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},
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/* End marker */
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{ -1, 0, 0, 0, 0, 0 }
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};
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void __init kirkwood_setup_cpu_mbus(void)
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{
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/*
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* Disable, clear and configure windows.
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*/
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orion_config_wins(&addr_map_cfg, addr_map_info);
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/*
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* Setup MBUS dram target info.
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*/
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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(void __iomem *) DDR_WINDOW_CPU_BASE);
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}
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