448 lines
16 KiB
C
448 lines
16 KiB
C
/* $Id: pgtable.h,v 1.156 2002/02/09 19:49:31 davem Exp $
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* pgtable.h: SpitFire page table operations.
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*
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* Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
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* Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#ifndef _SPARC64_PGTABLE_H
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#define _SPARC64_PGTABLE_H
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/* This file contains the functions and defines necessary to modify and use
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* the SpitFire page tables.
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*/
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#include <asm-generic/pgtable-nopud.h>
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#include <linux/config.h>
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#include <linux/compiler.h>
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#include <asm/types.h>
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#include <asm/spitfire.h>
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#include <asm/asi.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/const.h>
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/* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
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* The page copy blockops can use 0x2000000 to 0x10000000.
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* The PROM resides in an area spanning 0xf0000000 to 0x100000000.
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* The vmalloc area spans 0x100000000 to 0x200000000.
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* Since modules need to be in the lowest 32-bits of the address space,
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* we place them right before the OBP area from 0x10000000 to 0xf0000000.
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* There is a single static kernel PMD which maps from 0x0 to address
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* 0x400000000.
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*/
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#define TLBTEMP_BASE _AC(0x0000000002000000,UL)
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#define MODULES_VADDR _AC(0x0000000010000000,UL)
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#define MODULES_LEN _AC(0x00000000e0000000,UL)
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#define MODULES_END _AC(0x00000000f0000000,UL)
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#define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
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#define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
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#define VMALLOC_START _AC(0x0000000100000000,UL)
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#define VMALLOC_END _AC(0x0000000200000000,UL)
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/* XXX All of this needs to be rethought so we can take advantage
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* XXX cheetah's full 64-bit virtual address space, ie. no more hole
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* XXX in the middle like on spitfire. -DaveM
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*/
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/*
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* Given a virtual address, the lowest PAGE_SHIFT bits determine offset
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* into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
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* in the proper pagetable (the -3 is from the 8 byte ptes, and each page
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* table is a single page long). The next higher PMD_BITS determine pmd#
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* in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
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* since the pmd entries are 4 bytes, and each pmd page is a single page
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* long). Finally, the higher few bits determine pgde#.
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*/
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/* PMD_SHIFT determines the size of the area a second-level page
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* table can map
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*/
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#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
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#define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define PMD_BITS (PAGE_SHIFT - 2)
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
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#define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PGDIR_BITS (PAGE_SHIFT - 2)
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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/* Entries per page directory level. */
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#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
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#define PTRS_PER_PMD (1UL << PMD_BITS)
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#define PTRS_PER_PGD (1UL << PGDIR_BITS)
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/* Kernel has a separate 44bit address space. */
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#define FIRST_USER_ADDRESS 0
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#define pte_ERROR(e) __builtin_trap()
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#define pmd_ERROR(e) __builtin_trap()
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#define pgd_ERROR(e) __builtin_trap()
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#endif /* !(__ASSEMBLY__) */
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/* Spitfire/Cheetah TTE bits. */
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#define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
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#define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit up to date*/
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#define _PAGE_SZ4MB _AC(0x6000000000000000,UL) /* 4MB Page */
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#define _PAGE_SZ512K _AC(0x4000000000000000,UL) /* 512K Page */
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#define _PAGE_SZ64K _AC(0x2000000000000000,UL) /* 64K Page */
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#define _PAGE_SZ8K _AC(0x0000000000000000,UL) /* 8K Page */
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#define _PAGE_NFO _AC(0x1000000000000000,UL) /* No Fault Only */
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#define _PAGE_IE _AC(0x0800000000000000,UL) /* Invert Endianness */
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#define _PAGE_SOFT2 _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
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#define _PAGE_RES1 _AC(0x0002000000000000,UL) /* Reserved */
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#define _PAGE_SZ32MB _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
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#define _PAGE_SZ256MB _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
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#define _PAGE_SN _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
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#define _PAGE_RES2 _AC(0x0000780000000000,UL) /* Reserved */
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#define _PAGE_PADDR_SF _AC(0x000001FFFFFFE000,UL) /* (Spitfire) paddr[40:13]*/
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#define _PAGE_PADDR _AC(0x000007FFFFFFE000,UL) /* (Cheetah) paddr[42:13] */
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#define _PAGE_SOFT _AC(0x0000000000001F80,UL) /* Software bits */
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#define _PAGE_L _AC(0x0000000000000040,UL) /* Locked TTE */
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#define _PAGE_CP _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
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#define _PAGE_CV _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
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#define _PAGE_E _AC(0x0000000000000008,UL) /* side-Effect */
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#define _PAGE_P _AC(0x0000000000000004,UL) /* Privileged Page */
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#define _PAGE_W _AC(0x0000000000000002,UL) /* Writable */
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#define _PAGE_G _AC(0x0000000000000001,UL) /* Global */
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/* Here are the SpitFire software bits we use in the TTE's.
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*
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* WARNING: If you are going to try and start using some
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* of the soft2 bits, you will need to make
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* modifications to the swap entry implementation.
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* For example, one thing that could happen is that
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* swp_entry_to_pte() would BUG_ON() if you tried
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* to use one of the soft2 bits for _PAGE_FILE.
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*
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* Like other architectures, I have aliased _PAGE_FILE with
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* _PAGE_MODIFIED. This works because _PAGE_FILE is never
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* interpreted that way unless _PAGE_PRESENT is clear.
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*/
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#define _PAGE_EXEC _AC(0x0000000000001000,UL) /* Executable SW bit */
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#define _PAGE_MODIFIED _AC(0x0000000000000800,UL) /* Modified (dirty) */
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#define _PAGE_FILE _AC(0x0000000000000800,UL) /* Pagecache page */
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#define _PAGE_ACCESSED _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
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#define _PAGE_READ _AC(0x0000000000000200,UL) /* Readable SW Bit */
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#define _PAGE_WRITE _AC(0x0000000000000100,UL) /* Writable SW Bit */
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#define _PAGE_PRESENT _AC(0x0000000000000080,UL) /* Present */
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#if PAGE_SHIFT == 13
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#define _PAGE_SZBITS _PAGE_SZ8K
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#elif PAGE_SHIFT == 16
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#define _PAGE_SZBITS _PAGE_SZ64K
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#elif PAGE_SHIFT == 19
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#define _PAGE_SZBITS _PAGE_SZ512K
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#elif PAGE_SHIFT == 22
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#define _PAGE_SZBITS _PAGE_SZ4MB
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#else
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#error Wrong PAGE_SHIFT specified
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#endif
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#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
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#define _PAGE_SZHUGE _PAGE_SZ4MB
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
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#define _PAGE_SZHUGE _PAGE_SZ512K
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
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#define _PAGE_SZHUGE _PAGE_SZ64K
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#endif
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#define _PAGE_CACHE (_PAGE_CP | _PAGE_CV)
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#define __DIRTY_BITS (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W)
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#define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R)
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#define __PRIV_BITS _PAGE_P
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#define PAGE_NONE __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_CACHE)
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/* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */
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#define PAGE_SHARED __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
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__ACCESS_BITS | _PAGE_WRITE | _PAGE_EXEC)
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#define PAGE_COPY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
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__ACCESS_BITS | _PAGE_EXEC)
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#define PAGE_READONLY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
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__ACCESS_BITS | _PAGE_EXEC)
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#define PAGE_KERNEL __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
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__PRIV_BITS | \
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__ACCESS_BITS | __DIRTY_BITS | _PAGE_EXEC)
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#define PAGE_SHARED_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
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_PAGE_CACHE | \
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__ACCESS_BITS | _PAGE_WRITE)
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#define PAGE_COPY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
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_PAGE_CACHE | __ACCESS_BITS)
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#define PAGE_READONLY_NOEXEC __pgprot (_PAGE_PRESENT | _PAGE_VALID | \
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_PAGE_CACHE | __ACCESS_BITS)
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#define _PFN_MASK _PAGE_PADDR
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#define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | \
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__ACCESS_BITS | _PAGE_E)
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY_NOEXEC
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#define __P010 PAGE_COPY_NOEXEC
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#define __P011 PAGE_COPY_NOEXEC
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#define __P100 PAGE_READONLY
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#define __P101 PAGE_READONLY
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#define __P110 PAGE_COPY
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#define __P111 PAGE_COPY
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY_NOEXEC
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#define __S010 PAGE_SHARED_NOEXEC
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#define __S011 PAGE_SHARED_NOEXEC
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#define __S100 PAGE_READONLY
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#define __S101 PAGE_READONLY
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#define __S110 PAGE_SHARED
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#define __S111 PAGE_SHARED
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#ifndef __ASSEMBLY__
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extern unsigned long phys_base;
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extern unsigned long pfn_base;
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extern struct page *mem_map_zero;
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#define ZERO_PAGE(vaddr) (mem_map_zero)
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/* PFNs are real physical page numbers. However, mem_map only begins to record
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* per-page information starting at pfn_base. This is to handle systems where
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* the first physical page in the machine is at some huge physical address,
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* such as 4GB. This is common on a partitioned E10000, for example.
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*/
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#define pfn_pte(pfn, prot) \
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__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot) | _PAGE_SZBITS)
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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#define pte_pfn(x) ((pte_val(x) & _PAGE_PADDR)>>PAGE_SHIFT)
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
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{
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pte_t __pte;
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const unsigned long preserve_mask = (_PFN_MASK |
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_PAGE_MODIFIED | _PAGE_ACCESSED |
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_PAGE_CACHE | _PAGE_E |
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_PAGE_PRESENT | _PAGE_SZBITS);
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pte_val(__pte) = (pte_val(orig_pte) & preserve_mask) |
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(pgprot_val(new_prot) & ~preserve_mask);
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return __pte;
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}
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#define pmd_set(pmdp, ptep) \
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(pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
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#define pud_set(pudp, pmdp) \
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(pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
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#define __pmd_page(pmd) \
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((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
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#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
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#define pud_page(pud) \
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((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
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#define pte_none(pte) (!pte_val(pte))
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#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_bad(pmd) (0)
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#define pmd_present(pmd) (pmd_val(pmd) != 0U)
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#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
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#define pud_none(pud) (!pud_val(pud))
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#define pud_bad(pud) (0)
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#define pud_present(pud) (pud_val(pud) != 0U)
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#define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
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/* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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#define pte_read(pte) (pte_val(pte) & _PAGE_READ)
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#define pte_exec(pte) (pte_val(pte) & _PAGE_EXEC)
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#define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
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#define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED)
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#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
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#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W)))
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#define pte_rdprotect(pte) \
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(__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
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#define pte_mkclean(pte) \
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(__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
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#define pte_mkold(pte) \
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(__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
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/* Permanent address of a page. */
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#define __page_address(page) page_address(page)
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/* Be very careful when you change these three, they are delicate. */
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#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R))
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#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_WRITE))
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#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W))
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#define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_SZHUGE))
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/* to find an entry in a page-table-directory. */
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
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#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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/* extract the pgd cache used for optimizing the tlb miss
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* slow path when executing 32-bit compat processes
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*/
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#define get_pgd_cache(pgd) ((unsigned long) pgd_val(*pgd) << 11)
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/* Find an entry in the second-level page table.. */
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#define pmd_offset(pudp, address) \
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((pmd_t *) pud_page(*(pudp)) + \
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(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
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/* Find an entry in the third-level page table.. */
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#define pte_index(dir, address) \
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((pte_t *) __pmd_page(*(dir)) + \
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((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
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#define pte_offset_kernel pte_index
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#define pte_offset_map pte_index
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#define pte_offset_map_nested pte_index
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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/* Actual page table PTE updates. */
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extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
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static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
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{
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pte_t orig = *ptep;
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*ptep = pte;
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/* It is more efficient to let flush_tlb_kernel_range()
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* handle init_mm tlb flushes.
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*/
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if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
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tlb_batch_add(mm, addr, ptep, orig);
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}
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#define pte_clear(mm,addr,ptep) \
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set_pte_at((mm), (addr), (ptep), __pte(0UL))
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extern pgd_t swapper_pg_dir[2048];
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extern pmd_t swapper_low_pmd_dir[2048];
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extern void paging_init(void);
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extern unsigned long find_ecache_flush_span(unsigned long size);
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/* These do nothing with the way I have things setup. */
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#define mmu_lockarea(vaddr, len) (vaddr)
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#define mmu_unlockarea(vaddr, len) do { } while(0)
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struct vm_area_struct;
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extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
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/* Encode and de-code a swap entry */
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#define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
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#define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
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#define __swp_entry(type, offset) \
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( (swp_entry_t) \
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{ \
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(((long)(type) << PAGE_SHIFT) | \
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((long)(offset) << (PAGE_SHIFT + 8UL))) \
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} )
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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/* File offset in PTE support. */
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#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
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#define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define pgoff_to_pte(off) (__pte(((off) << PAGE_SHIFT) | _PAGE_FILE))
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#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
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extern unsigned long prom_virt_to_phys(unsigned long, int *);
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static __inline__ unsigned long
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sun4u_get_pte (unsigned long addr)
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{
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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if (addr >= PAGE_OFFSET)
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return addr & _PAGE_PADDR;
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if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
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return prom_virt_to_phys(addr, NULL);
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pgdp = pgd_offset_k(addr);
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pudp = pud_offset(pgdp, addr);
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pmdp = pmd_offset(pudp, addr);
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ptep = pte_offset_kernel(pmdp, addr);
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return pte_val(*ptep) & _PAGE_PADDR;
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}
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static __inline__ unsigned long
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__get_phys (unsigned long addr)
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{
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return sun4u_get_pte (addr);
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}
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static __inline__ int
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__get_iospace (unsigned long addr)
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{
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return ((sun4u_get_pte (addr) & 0xf0000000) >> 28);
|
|
}
|
|
|
|
extern unsigned long *sparc64_valid_addr_bitmap;
|
|
|
|
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
|
|
#define kern_addr_valid(addr) \
|
|
(test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
|
|
|
|
extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
|
|
unsigned long pfn,
|
|
unsigned long size, pgprot_t prot);
|
|
|
|
/* Clear virtual and physical cachability, set side-effect bit. */
|
|
#define pgprot_noncached(prot) \
|
|
(__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \
|
|
_PAGE_E))
|
|
|
|
/*
|
|
* For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
|
|
* its high 4 bits. These macros/functions put it there or get it from there.
|
|
*/
|
|
#define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
|
|
#define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
|
|
#define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
|
|
|
|
#include <asm-generic/pgtable.h>
|
|
|
|
/* We provide our own get_unmapped_area to cope with VA holes for userland */
|
|
#define HAVE_ARCH_UNMAPPED_AREA
|
|
|
|
/* We provide a special get_unmapped_area for framebuffer mmaps to try and use
|
|
* the largest alignment possible such that larget PTEs can be used.
|
|
*/
|
|
extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
|
|
unsigned long, unsigned long,
|
|
unsigned long);
|
|
#define HAVE_ARCH_FB_UNMAPPED_AREA
|
|
|
|
/*
|
|
* No page table caches to initialise
|
|
*/
|
|
#define pgtable_cache_init() do { } while (0)
|
|
|
|
extern void check_pgt_cache(void);
|
|
|
|
#endif /* !(__ASSEMBLY__) */
|
|
|
|
#endif /* !(_SPARC64_PGTABLE_H) */
|