306 lines
10 KiB
C
306 lines
10 KiB
C
/* Bt832 CMOS Camera Video Processor (VP)
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The Bt832 CMOS Camera Video Processor chip connects a Quartsight CMOS
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color digital camera directly to video capture devices via an 8-bit,
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4:2:2 YUV or YCrCb video interface.
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i2c addresses: 0x88 or 0x8a
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*/
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/* The 64 registers: */
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// Input Processor
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#define BT832_OFFSET 0
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#define BT832_RCOMP 1
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#define BT832_G1COMP 2
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#define BT832_G2COMP 3
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#define BT832_BCOMP 4
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// Exposures:
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#define BT832_FINEH 5
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#define BT832_FINEL 6
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#define BT832_COARSEH 7
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#define BT832_COARSEL 8
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#define BT832_CAMGAIN 9
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// Main Processor:
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#define BT832_M00 10
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#define BT832_M01 11
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#define BT832_M02 12
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#define BT832_M10 13
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#define BT832_M11 14
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#define BT832_M12 15
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#define BT832_M20 16
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#define BT832_M21 17
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#define BT832_M22 18
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#define BT832_APCOR 19
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#define BT832_GAMCOR 20
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// Level Accumulator Inputs
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#define BT832_VPCONTROL2 21
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#define BT832_ZONECODE0 22
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#define BT832_ZONECODE1 23
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#define BT832_ZONECODE2 24
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#define BT832_ZONECODE3 25
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// Level Accumulator Outputs:
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#define BT832_RACC 26
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#define BT832_GACC 27
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#define BT832_BACC 28
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#define BT832_BLACKACC 29
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#define BT832_EXP_AGC 30
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#define BT832_LACC0 31
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#define BT832_LACC1 32
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#define BT832_LACC2 33
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#define BT832_LACC3 34
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#define BT832_LACC4 35
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#define BT832_LACC5 36
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#define BT832_LACC6 37
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#define BT832_LACC7 38
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// System:
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#define BT832_VP_CONTROL0 39
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#define BT832_VP_CONTROL1 40
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#define BT832_THRESH 41
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#define BT832_VP_TESTCONTROL0 42
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#define BT832_VP_DMCODE 43
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#define BT832_ACB_CONFIG 44
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#define BT832_ACB_GNBASE 45
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#define BT832_ACB_MU 46
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#define BT832_CAM_TEST0 47
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#define BT832_AEC_CONFIG 48
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#define BT832_AEC_TL 49
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#define BT832_AEC_TC 50
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#define BT832_AEC_TH 51
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// Status:
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#define BT832_VP_STATUS 52
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#define BT832_VP_LINECOUNT 53
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#define BT832_CAM_DEVICEL 54 // e.g. 0x19
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#define BT832_CAM_DEVICEH 55 // e.g. 0x40 == 0x194 Mask0, 0x194 = 404 decimal (VVL-404 camera)
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#define BT832_CAM_STATUS 56
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#define BT832_56_CAMERA_PRESENT 0x20
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//Camera Setups:
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#define BT832_CAM_SETUP0 57
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#define BT832_CAM_SETUP1 58
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#define BT832_CAM_SETUP2 59
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#define BT832_CAM_SETUP3 60
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// System:
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#define BT832_DEFCOR 61
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#define BT832_VP_TESTCONTROL1 62
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#define BT832_DEVICE_ID 63
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# define BT832_DEVICE_ID__31 0x31 // Bt832 has ID 0x31
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/* STMicroelectronivcs VV5404 camera module
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i2c: 0x20: sensor address
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i2c: 0xa0: eeprom for ccd defect map
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*/
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#define VV5404_device_h 0x00 // 0x19
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#define VV5404_device_l 0x01 // 0x40
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#define VV5404_status0 0x02
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#define VV5404_linecountc 0x03 // current line counter
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#define VV5404_linecountl 0x04
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#define VV5404_setup0 0x10
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#define VV5404_setup1 0x11
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#define VV5404_setup2 0x12
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#define VV5404_setup4 0x14
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#define VV5404_setup5 0x15
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#define VV5404_fine_h 0x20 // fine exposure
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#define VV5404_fine_l 0x21
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#define VV5404_coarse_h 0x22 //coarse exposure
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#define VV5404_coarse_l 0x23
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#define VV5404_gain 0x24 // ADC pre-amp gain setting
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#define VV5404_clk_div 0x25
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#define VV5404_cr 0x76 // control register
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#define VV5404_as0 0x77 // ADC setup register
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// IOCTL
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#define BT832_HEXDUMP _IOR('b',1,int)
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#define BT832_REATTACH _IOR('b',2,int)
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/* from BT8x8VXD/capdrv/dialogs.cpp */
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/*
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typedef enum { SVI, Logitech, Rockwell } CAMERA;
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static COMBOBOX_ENTRY gwCameraOptions[] =
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{
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{ SVI, "Silicon Vision 512N" },
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{ Logitech, "Logitech VideoMan 1.3" },
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{ Rockwell, "Rockwell QuartzSight PCI 1.0" }
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};
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// SRAM table values
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//===========================================================================
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typedef enum { TGB_NTSC624, TGB_NTSC780, TGB_NTSC858, TGB_NTSC392 } TimeGenByte;
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BYTE SRAMTable[][ 60 ] =
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{
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// TGB_NTSC624
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{
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0x33, // size of table = 51
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0x0E, 0xC0, 0x00, 0x00, 0x90, 0x02, 0x03, 0x10, 0x03, 0x06,
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0x10, 0x04, 0x12, 0x12, 0x05, 0x02, 0x13, 0x04, 0x19, 0x00,
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0x04, 0x39, 0x00, 0x06, 0x59, 0x08, 0x03, 0x85, 0x08, 0x07,
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0x03, 0x50, 0x00, 0x91, 0x40, 0x00, 0x11, 0x01, 0x01, 0x4D,
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0x0D, 0x02, 0x03, 0x11, 0x01, 0x05, 0x37, 0x00, 0x37, 0x21, 0x00
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},
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// TGB_NTSC780
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{
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0x33, // size of table = 51
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0x0e, 0xc0, 0x00, 0x00, 0x90, 0xe2, 0x03, 0x10, 0x03, 0x06,
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0x10, 0x34, 0x12, 0x12, 0x65, 0x02, 0x13, 0x24, 0x19, 0x00,
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0x24, 0x39, 0x00, 0x96, 0x59, 0x08, 0x93, 0x85, 0x08, 0x97,
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0x03, 0x50, 0x50, 0xaf, 0x40, 0x30, 0x5f, 0x01, 0xf1, 0x7f,
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0x0d, 0xf2, 0x03, 0x11, 0xf1, 0x05, 0x37, 0x30, 0x85, 0x21, 0x50
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},
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// TGB_NTSC858
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{
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0x33, // size of table = 51
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0x0c, 0xc0, 0x00, 0x00, 0x90, 0xc2, 0x03, 0x10, 0x03, 0x06,
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0x10, 0x34, 0x12, 0x12, 0x65, 0x02, 0x13, 0x24, 0x19, 0x00,
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0x24, 0x39, 0x00, 0x96, 0x59, 0x08, 0x93, 0x83, 0x08, 0x97,
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0x03, 0x50, 0x30, 0xc0, 0x40, 0x30, 0x86, 0x01, 0x01, 0xa6,
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0x0d, 0x62, 0x03, 0x11, 0x61, 0x05, 0x37, 0x30, 0xac, 0x21, 0x50
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},
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// TGB_NTSC392
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// This table has been modified to be used for Fusion Rev D
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{
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0x2A, // size of table = 42
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0x06, 0x08, 0x04, 0x0a, 0xc0, 0x00, 0x18, 0x08, 0x03, 0x24,
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0x08, 0x07, 0x02, 0x90, 0x02, 0x08, 0x10, 0x04, 0x0c, 0x10,
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0x05, 0x2c, 0x11, 0x04, 0x55, 0x48, 0x00, 0x05, 0x50, 0x00,
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0xbf, 0x0c, 0x02, 0x2f, 0x3d, 0x00, 0x2f, 0x3f, 0x00, 0xc3,
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0x20, 0x00
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}
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};
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//===========================================================================
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// This is the structure of the camera specifications
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//===========================================================================
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typedef struct tag_cameraSpec
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{
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SignalFormat signal; // which digital signal format the camera has
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VideoFormat vidFormat; // video standard
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SyncVideoRef syncRef; // which sync video reference is used
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State syncOutput; // enable sync output for sync video input?
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DecInputClk iClk; // which input clock is used
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TimeGenByte tgb; // which timing generator byte does the camera use
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int HReset; // select 64, 48, 32, or 16 CLKx1 for HReset
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PLLFreq pllFreq; // what synthesized frequency to set PLL to
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VSIZEPARMS vSize; // video size the camera produces
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int lineCount; // expected total number of half-line per frame - 1
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BOOL interlace; // interlace signal?
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} CameraSpec;
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//===========================================================================
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// <UPDATE REQUIRED>
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// Camera specifications database. Update this table whenever camera spec
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// has been changed or added/deleted supported camera models
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//===========================================================================
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static CameraSpec dbCameraSpec[ N_CAMERAOPTIONS ] =
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{ // Silicon Vision 512N
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{ Signal_CCIR656, VFormat_NTSC, VRef_alignedCb, Off, DecClk_GPCLK, TGB_NTSC624, 64, KHz19636,
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// Clkx1_HACTIVE, Clkx1_HDELAY, VActive, VDelay, linesPerField; lineCount, Interlace
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{ 512, 0x64, 480, 0x13, 240 }, 0, TRUE
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},
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// Logitech VideoMan 1.3
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{ Signal_CCIR656, VFormat_NTSC, VRef_alignedCb, Off, DecClk_GPCLK, TGB_NTSC780, 64, KHz24545,
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// Clkx1_HACTIVE, Clkx1_HDELAY, VActive, VDelay, linesPerField; lineCount, Interlace
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{ 640, 0x80, 480, 0x1A, 240 }, 0, TRUE
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},
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// Rockwell QuartzSight
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// Note: Fusion Rev D (rev ID 0x02) and later supports 16 pixels for HReset which is preferable.
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// Use 32 for earlier version of hardware. Clkx1_HDELAY also changed from 0x27 to 0x20.
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{ Signal_CCIR656, VFormat_NTSC, VRef_alignedCb, Off, DecClk_GPCLK, TGB_NTSC392, 16, KHz28636,
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// Clkx1_HACTIVE, Clkx1_HDELAY, VActive, VDelay, linesPerField; lineCount, Interlace
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{ 352, 0x20, 576, 0x08, 288 }, 607, FALSE
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}
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};
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*/
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/*
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The corresponding APIs required to be invoked are:
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SetConnector( ConCamera, TRUE/FALSE );
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SetSignalFormat( spec.signal );
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SetVideoFormat( spec.vidFormat );
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SetSyncVideoRef( spec.syncRef );
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SetEnableSyncOutput( spec.syncOutput );
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SetTimGenByte( SRAMTable[ spec.tgb ], SRAMTableSize[ spec.tgb ] );
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SetHReset( spec.HReset );
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SetPLL( spec.pllFreq );
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SetDecInputClock( spec.iClk );
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SetVideoInfo( spec.vSize );
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SetTotalLineCount( spec.lineCount );
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SetInterlaceMode( spec.interlace );
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*/
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/* from web:
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Video Sampling
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Digital video is a sampled form of analog video. The most common sampling schemes in use today are:
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Pixel Clock Horiz Horiz Vert
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Rate Total Active
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NTSC square pixel 12.27 MHz 780 640 525
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NTSC CCIR-601 13.5 MHz 858 720 525
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NTSC 4FSc 14.32 MHz 910 768 525
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PAL square pixel 14.75 MHz 944 768 625
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PAL CCIR-601 13.5 MHz 864 720 625
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PAL 4FSc 17.72 MHz 1135 948 625
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For the CCIR-601 standards, the sampling is based on a static orthogonal sampling grid. The luminance component (Y) is sampled at 13.5 MHz, while the two color difference signals, Cr and Cb are sampled at half that, or 6.75 MHz. The Cr and Cb samples are colocated with alternate Y samples, and they are taken at the same position on each line, such that one sample is coincident with the 50% point of the falling edge of analog sync. The samples are coded to either 8 or 10 bits per component.
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*/
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/* from DScaler:*/
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/*
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//===========================================================================
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// CCIR656 Digital Input Support: The tables were taken from DScaler proyect
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//
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// 13 Dec 2000 - Michael Eskin, Conexant Systems - Initial version
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//
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//===========================================================================
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// Timing generator SRAM table values for CCIR601 720x480 NTSC
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//===========================================================================
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// For NTSC CCIR656
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BYTE BtCard::SRAMTable_NTSC[] =
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{
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// SRAM Timing Table for NTSC
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0x0c, 0xc0, 0x00,
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0x00, 0x90, 0xc2,
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0x03, 0x10, 0x03,
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0x06, 0x10, 0x34,
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0x12, 0x12, 0x65,
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0x02, 0x13, 0x24,
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0x19, 0x00, 0x24,
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0x39, 0x00, 0x96,
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0x59, 0x08, 0x93,
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0x83, 0x08, 0x97,
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0x03, 0x50, 0x30,
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0xc0, 0x40, 0x30,
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0x86, 0x01, 0x01,
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0xa6, 0x0d, 0x62,
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0x03, 0x11, 0x61,
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0x05, 0x37, 0x30,
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0xac, 0x21, 0x50
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};
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//===========================================================================
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// Timing generator SRAM table values for CCIR601 720x576 NTSC
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//===========================================================================
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// For PAL CCIR656
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BYTE BtCard::SRAMTable_PAL[] =
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{
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// SRAM Timing Table for PAL
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0x36, 0x11, 0x01,
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0x00, 0x90, 0x02,
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0x05, 0x10, 0x04,
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0x16, 0x14, 0x05,
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0x11, 0x00, 0x04,
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0x12, 0xc0, 0x00,
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0x31, 0x00, 0x06,
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0x51, 0x08, 0x03,
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0x89, 0x08, 0x07,
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0xc0, 0x44, 0x00,
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0x81, 0x01, 0x01,
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0xa9, 0x0d, 0x02,
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0x02, 0x50, 0x03,
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0x37, 0x3d, 0x00,
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0xaf, 0x21, 0x00,
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};
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*/
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