364 lines
9.5 KiB
C
364 lines
9.5 KiB
C
/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/nl80211.h>
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#include <linux/pci.h>
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#include <linux/pci-aspm.h>
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#include <linux/etherdevice.h>
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#include "../ath.h"
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#include "ath5k.h"
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#include "debug.h"
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#include "base.h"
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#include "reg.h"
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/* Known PCI ids */
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static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
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{ PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
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{ PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
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{ PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
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{ PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
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{ PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
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{ PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
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{ PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
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{ PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
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{ PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */
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{ PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */
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{ PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */
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{ PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */
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{ PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */
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{ PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */
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{ PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
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{ PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
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{ PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
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{ PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
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{ 0 }
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};
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MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
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/* return bus cachesize in 4B word units */
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static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
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{
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struct ath5k_hw *ah = (struct ath5k_hw *) common->priv;
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u8 u8tmp;
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pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
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*csz = (int)u8tmp;
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/*
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* This check was put in to avoid "unpleasant" consequences if
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* the bootrom has not fully initialized all PCI devices.
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* Sometimes the cache line size register is not set
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*/
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if (*csz == 0)
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*csz = L1_CACHE_BYTES >> 2; /* Use the default size */
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}
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/*
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* Read from eeprom
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*/
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static bool
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ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
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{
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struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
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u32 status, timeout;
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/*
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* Initialize EEPROM access
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*/
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if (ah->ah_version == AR5K_AR5210) {
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AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
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(void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
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} else {
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ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
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AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
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AR5K_EEPROM_CMD_READ);
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}
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for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
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status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
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if (status & AR5K_EEPROM_STAT_RDDONE) {
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if (status & AR5K_EEPROM_STAT_RDERR)
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return false;
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*data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
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0xffff);
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return true;
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}
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udelay(15);
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}
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return false;
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}
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int ath5k_hw_read_srev(struct ath5k_hw *ah)
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{
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ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
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return 0;
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}
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/*
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* Read the MAC address from eeprom or platform_data
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*/
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static int ath5k_pci_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
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{
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u8 mac_d[ETH_ALEN] = {};
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u32 total, offset;
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u16 data;
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int octet;
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AR5K_EEPROM_READ(0x20, data);
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for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
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AR5K_EEPROM_READ(offset, data);
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total += data;
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mac_d[octet + 1] = data & 0xff;
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mac_d[octet] = data >> 8;
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octet += 2;
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}
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if (!total || total == 3 * 0xffff)
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return -EINVAL;
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memcpy(mac, mac_d, ETH_ALEN);
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return 0;
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}
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/* Common ath_bus_opts structure */
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static const struct ath_bus_ops ath_pci_bus_ops = {
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.ath_bus_type = ATH_PCI,
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.read_cachesize = ath5k_pci_read_cachesize,
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.eeprom_read = ath5k_pci_eeprom_read,
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.eeprom_read_mac = ath5k_pci_eeprom_read_mac,
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};
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/********************\
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* PCI Initialization *
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\********************/
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static int __devinit
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ath5k_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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void __iomem *mem;
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struct ath5k_hw *ah;
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struct ieee80211_hw *hw;
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int ret;
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u8 csz;
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/*
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* L0s needs to be disabled on all ath5k cards.
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*
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* For distributions shipping with CONFIG_PCIEASPM (this will be enabled
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* by default in the future in 2.6.36) this will also mean both L1 and
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* L0s will be disabled when a pre 1.1 PCIe device is detected. We do
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* know L1 works correctly even for all ath5k pre 1.1 PCIe devices
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* though but cannot currently undue the effect of a blacklist, for
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* details you can read pcie_aspm_sanity_check() and see how it adjusts
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* the device link capability.
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*
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* It may be possible in the future to implement some PCI API to allow
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* drivers to override blacklists for pre 1.1 PCIe but for now it is
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* best to accept that both L0s and L1 will be disabled completely for
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* distributions shipping with CONFIG_PCIEASPM rather than having this
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* issue present. Motivation for adding this new API will be to help
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* with power consumption for some of these devices.
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*/
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pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
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ret = pci_enable_device(pdev);
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if (ret) {
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dev_err(&pdev->dev, "can't enable device\n");
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goto err;
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}
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/* XXX 32-bit addressing only */
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ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (ret) {
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dev_err(&pdev->dev, "32-bit DMA not available\n");
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goto err_dis;
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}
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/*
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* Cache line size is used to size and align various
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* structures used to communicate with the hardware.
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*/
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
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if (csz == 0) {
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/*
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* Linux 2.4.18 (at least) writes the cache line size
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* register as a 16-bit wide register which is wrong.
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* We must have this setup properly for rx buffer
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* DMA to work so force a reasonable value here if it
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* comes up zero.
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*/
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csz = L1_CACHE_BYTES >> 2;
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
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}
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/*
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* The default setting of latency timer yields poor results,
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* set it to the value used by other systems. It may be worth
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* tweaking this setting more.
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*/
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
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/* Enable bus mastering */
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pci_set_master(pdev);
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/*
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* Disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state.
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*/
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pci_write_config_byte(pdev, 0x41, 0);
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ret = pci_request_region(pdev, 0, "ath5k");
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if (ret) {
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dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
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goto err_dis;
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}
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mem = pci_iomap(pdev, 0, 0);
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if (!mem) {
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dev_err(&pdev->dev, "cannot remap PCI memory region\n");
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ret = -EIO;
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goto err_reg;
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}
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/*
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* Allocate hw (mac80211 main struct)
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* and hw->priv (driver private data)
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*/
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hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops);
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if (hw == NULL) {
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dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
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ret = -ENOMEM;
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goto err_map;
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}
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dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
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ah = hw->priv;
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ah->hw = hw;
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ah->pdev = pdev;
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ah->dev = &pdev->dev;
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ah->irq = pdev->irq;
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ah->devid = id->device;
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ah->iobase = mem; /* So we can unmap it on detach */
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/* Initialize */
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ret = ath5k_init_ah(ah, &ath_pci_bus_ops);
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if (ret)
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goto err_free;
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/* Set private data */
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pci_set_drvdata(pdev, hw);
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return 0;
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err_free:
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ieee80211_free_hw(hw);
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err_map:
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pci_iounmap(pdev, mem);
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err_reg:
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pci_release_region(pdev, 0);
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err_dis:
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pci_disable_device(pdev);
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err:
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return ret;
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}
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static void __devexit
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ath5k_pci_remove(struct pci_dev *pdev)
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{
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath5k_hw *ah = hw->priv;
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ath5k_deinit_ah(ah);
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pci_iounmap(pdev, ah->iobase);
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pci_release_region(pdev, 0);
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pci_disable_device(pdev);
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ieee80211_free_hw(hw);
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}
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#ifdef CONFIG_PM_SLEEP
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static int ath5k_pci_suspend(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath5k_hw *ah = hw->priv;
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ath5k_led_off(ah);
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return 0;
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}
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static int ath5k_pci_resume(struct device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath5k_hw *ah = hw->priv;
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/*
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* Suspend/Resume resets the PCI configuration space, so we have to
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* re-disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state
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*/
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pci_write_config_byte(pdev, 0x41, 0);
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ath5k_led_enable(ah);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
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#define ATH5K_PM_OPS (&ath5k_pm_ops)
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#else
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#define ATH5K_PM_OPS NULL
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#endif /* CONFIG_PM_SLEEP */
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static struct pci_driver ath5k_pci_driver = {
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.name = KBUILD_MODNAME,
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.id_table = ath5k_pci_id_table,
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.probe = ath5k_pci_probe,
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.remove = __devexit_p(ath5k_pci_remove),
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.driver.pm = ATH5K_PM_OPS,
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};
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/*
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* Module init/exit functions
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*/
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static int __init
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init_ath5k_pci(void)
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{
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int ret;
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ret = pci_register_driver(&ath5k_pci_driver);
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if (ret) {
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printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
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return ret;
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}
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return 0;
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}
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static void __exit
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exit_ath5k_pci(void)
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{
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pci_unregister_driver(&ath5k_pci_driver);
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}
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module_init(init_ath5k_pci);
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module_exit(exit_ath5k_pci);
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