535 lines
13 KiB
C
535 lines
13 KiB
C
/*
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* Freescale/Motorola Coldfire Queued SPI driver
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*
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* Copyright 2010 Steven King <sfking@fdwdc.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/errno.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/spi/spi.h>
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#include <linux/pm_runtime.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfqspi.h>
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#define DRIVER_NAME "mcfqspi"
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#define MCFQSPI_BUSCLK (MCF_BUSCLK / 2)
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#define MCFQSPI_QMR 0x00
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#define MCFQSPI_QMR_MSTR 0x8000
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#define MCFQSPI_QMR_CPOL 0x0200
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#define MCFQSPI_QMR_CPHA 0x0100
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#define MCFQSPI_QDLYR 0x04
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#define MCFQSPI_QDLYR_SPE 0x8000
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#define MCFQSPI_QWR 0x08
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#define MCFQSPI_QWR_HALT 0x8000
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#define MCFQSPI_QWR_WREN 0x4000
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#define MCFQSPI_QWR_CSIV 0x1000
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#define MCFQSPI_QIR 0x0C
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#define MCFQSPI_QIR_WCEFB 0x8000
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#define MCFQSPI_QIR_ABRTB 0x4000
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#define MCFQSPI_QIR_ABRTL 0x1000
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#define MCFQSPI_QIR_WCEFE 0x0800
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#define MCFQSPI_QIR_ABRTE 0x0400
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#define MCFQSPI_QIR_SPIFE 0x0100
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#define MCFQSPI_QIR_WCEF 0x0008
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#define MCFQSPI_QIR_ABRT 0x0004
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#define MCFQSPI_QIR_SPIF 0x0001
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#define MCFQSPI_QAR 0x010
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#define MCFQSPI_QAR_TXBUF 0x00
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#define MCFQSPI_QAR_RXBUF 0x10
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#define MCFQSPI_QAR_CMDBUF 0x20
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#define MCFQSPI_QDR 0x014
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#define MCFQSPI_QCR 0x014
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#define MCFQSPI_QCR_CONT 0x8000
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#define MCFQSPI_QCR_BITSE 0x4000
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#define MCFQSPI_QCR_DT 0x2000
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struct mcfqspi {
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void __iomem *iobase;
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int irq;
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struct clk *clk;
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struct mcfqspi_cs_control *cs_control;
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wait_queue_head_t waitq;
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};
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static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
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{
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writew(val, mcfqspi->iobase + MCFQSPI_QMR);
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}
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static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
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{
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writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
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}
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static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
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{
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return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
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}
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static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
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{
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writew(val, mcfqspi->iobase + MCFQSPI_QWR);
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}
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static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
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{
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writew(val, mcfqspi->iobase + MCFQSPI_QIR);
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}
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static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
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{
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writew(val, mcfqspi->iobase + MCFQSPI_QAR);
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}
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static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
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{
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writew(val, mcfqspi->iobase + MCFQSPI_QDR);
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}
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static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
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{
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return readw(mcfqspi->iobase + MCFQSPI_QDR);
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}
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static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
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bool cs_high)
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{
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mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
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}
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static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
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bool cs_high)
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{
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mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
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}
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static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
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{
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return (mcfqspi->cs_control->setup) ?
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mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
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}
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static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
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{
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if (mcfqspi->cs_control->teardown)
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mcfqspi->cs_control->teardown(mcfqspi->cs_control);
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}
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static u8 mcfqspi_qmr_baud(u32 speed_hz)
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{
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return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
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}
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static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
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{
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return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
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}
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static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
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{
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struct mcfqspi *mcfqspi = dev_id;
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/* clear interrupt */
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mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
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wake_up(&mcfqspi->waitq);
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return IRQ_HANDLED;
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}
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static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
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const u8 *txbuf, u8 *rxbuf)
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{
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unsigned i, n, offset = 0;
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n = min(count, 16u);
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mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
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for (i = 0; i < n; ++i)
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mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
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mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
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if (txbuf)
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for (i = 0; i < n; ++i)
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mcfqspi_wr_qdr(mcfqspi, *txbuf++);
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else
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for (i = 0; i < count; ++i)
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mcfqspi_wr_qdr(mcfqspi, 0);
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count -= n;
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if (count) {
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u16 qwr = 0xf08;
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mcfqspi_wr_qwr(mcfqspi, 0x700);
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mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
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do {
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wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
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mcfqspi_wr_qwr(mcfqspi, qwr);
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mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
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if (rxbuf) {
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mcfqspi_wr_qar(mcfqspi,
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MCFQSPI_QAR_RXBUF + offset);
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for (i = 0; i < 8; ++i)
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*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
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}
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n = min(count, 8u);
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if (txbuf) {
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mcfqspi_wr_qar(mcfqspi,
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MCFQSPI_QAR_TXBUF + offset);
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for (i = 0; i < n; ++i)
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mcfqspi_wr_qdr(mcfqspi, *txbuf++);
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}
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qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
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offset ^= 8;
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count -= n;
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} while (count);
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wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
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mcfqspi_wr_qwr(mcfqspi, qwr);
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mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
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if (rxbuf) {
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mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
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for (i = 0; i < 8; ++i)
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*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
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offset ^= 8;
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}
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} else {
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mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
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mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
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}
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wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
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if (rxbuf) {
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mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
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for (i = 0; i < n; ++i)
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*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
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}
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}
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static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
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const u16 *txbuf, u16 *rxbuf)
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{
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unsigned i, n, offset = 0;
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n = min(count, 16u);
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mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
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for (i = 0; i < n; ++i)
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mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
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mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
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if (txbuf)
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for (i = 0; i < n; ++i)
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mcfqspi_wr_qdr(mcfqspi, *txbuf++);
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else
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for (i = 0; i < count; ++i)
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mcfqspi_wr_qdr(mcfqspi, 0);
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count -= n;
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if (count) {
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u16 qwr = 0xf08;
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mcfqspi_wr_qwr(mcfqspi, 0x700);
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mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
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do {
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wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
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mcfqspi_wr_qwr(mcfqspi, qwr);
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mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
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if (rxbuf) {
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mcfqspi_wr_qar(mcfqspi,
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MCFQSPI_QAR_RXBUF + offset);
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for (i = 0; i < 8; ++i)
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*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
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}
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n = min(count, 8u);
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if (txbuf) {
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mcfqspi_wr_qar(mcfqspi,
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MCFQSPI_QAR_TXBUF + offset);
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for (i = 0; i < n; ++i)
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mcfqspi_wr_qdr(mcfqspi, *txbuf++);
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}
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qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
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offset ^= 8;
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count -= n;
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} while (count);
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wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
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mcfqspi_wr_qwr(mcfqspi, qwr);
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mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
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if (rxbuf) {
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mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
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for (i = 0; i < 8; ++i)
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*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
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offset ^= 8;
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}
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} else {
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mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
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mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
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}
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wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
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if (rxbuf) {
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mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
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for (i = 0; i < n; ++i)
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*rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
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}
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}
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static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
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{
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struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
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bool cs_high = spi->mode & SPI_CS_HIGH;
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if (enable)
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mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
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else
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mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
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}
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static int mcfqspi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
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u16 qmr = MCFQSPI_QMR_MSTR;
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qmr |= t->bits_per_word << 10;
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if (spi->mode & SPI_CPHA)
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qmr |= MCFQSPI_QMR_CPHA;
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if (spi->mode & SPI_CPOL)
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qmr |= MCFQSPI_QMR_CPOL;
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qmr |= mcfqspi_qmr_baud(t->speed_hz);
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mcfqspi_wr_qmr(mcfqspi, qmr);
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mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
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if (t->bits_per_word == 8)
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mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
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else
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mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
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t->rx_buf);
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mcfqspi_wr_qir(mcfqspi, 0);
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return 0;
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}
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static int mcfqspi_setup(struct spi_device *spi)
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{
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mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
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spi->chip_select, spi->mode & SPI_CS_HIGH);
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dev_dbg(&spi->dev,
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"bits per word %d, chip select %d, speed %d KHz\n",
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spi->bits_per_word, spi->chip_select,
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(MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
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/ 1000);
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return 0;
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}
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static int mcfqspi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct mcfqspi *mcfqspi;
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struct resource *res;
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struct mcfqspi_platform_data *pdata;
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int status;
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pdata = dev_get_platdata(&pdev->dev);
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if (!pdata) {
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dev_dbg(&pdev->dev, "platform data is missing\n");
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return -ENOENT;
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}
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if (!pdata->cs_control) {
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dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
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return -EINVAL;
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}
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master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
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if (master == NULL) {
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dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
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return -ENOMEM;
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}
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mcfqspi = spi_master_get_devdata(master);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mcfqspi->iobase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mcfqspi->iobase)) {
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status = PTR_ERR(mcfqspi->iobase);
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goto fail0;
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}
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mcfqspi->irq = platform_get_irq(pdev, 0);
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if (mcfqspi->irq < 0) {
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dev_dbg(&pdev->dev, "platform_get_irq failed\n");
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status = -ENXIO;
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goto fail0;
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}
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status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
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0, pdev->name, mcfqspi);
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if (status) {
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dev_dbg(&pdev->dev, "request_irq failed\n");
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goto fail0;
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}
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mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
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if (IS_ERR(mcfqspi->clk)) {
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dev_dbg(&pdev->dev, "clk_get failed\n");
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status = PTR_ERR(mcfqspi->clk);
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goto fail0;
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}
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clk_enable(mcfqspi->clk);
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master->bus_num = pdata->bus_num;
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master->num_chipselect = pdata->num_chipselect;
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mcfqspi->cs_control = pdata->cs_control;
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status = mcfqspi_cs_setup(mcfqspi);
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if (status) {
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dev_dbg(&pdev->dev, "error initializing cs_control\n");
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goto fail1;
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}
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init_waitqueue_head(&mcfqspi->waitq);
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master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
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master->setup = mcfqspi_setup;
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master->set_cs = mcfqspi_set_cs;
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master->transfer_one = mcfqspi_transfer_one;
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master->auto_runtime_pm = true;
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platform_set_drvdata(pdev, master);
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status = devm_spi_register_master(&pdev->dev, master);
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if (status) {
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dev_dbg(&pdev->dev, "spi_register_master failed\n");
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goto fail2;
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}
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pm_runtime_enable(&pdev->dev);
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dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
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return 0;
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fail2:
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mcfqspi_cs_teardown(mcfqspi);
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fail1:
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clk_disable(mcfqspi->clk);
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fail0:
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spi_master_put(master);
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dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
|
|
|
|
return status;
|
|
}
|
|
|
|
static int mcfqspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
/* disable the hardware (set the baud rate to 0) */
|
|
mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
|
|
|
|
mcfqspi_cs_teardown(mcfqspi);
|
|
clk_disable(mcfqspi->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int mcfqspi_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
ret = spi_master_suspend(master);
|
|
if (ret)
|
|
return ret;
|
|
|
|
clk_disable(mcfqspi->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mcfqspi_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
|
|
|
clk_enable(mcfqspi->clk);
|
|
|
|
return spi_master_resume(master);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
static int mcfqspi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
|
|
|
clk_disable(mcfqspi->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mcfqspi_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
|
|
|
clk_enable(mcfqspi->clk);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops mcfqspi_pm = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
|
|
SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
|
|
NULL)
|
|
};
|
|
|
|
static struct platform_driver mcfqspi_driver = {
|
|
.driver.name = DRIVER_NAME,
|
|
.driver.owner = THIS_MODULE,
|
|
.driver.pm = &mcfqspi_pm,
|
|
.probe = mcfqspi_probe,
|
|
.remove = mcfqspi_remove,
|
|
};
|
|
module_platform_driver(mcfqspi_driver);
|
|
|
|
MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
|
|
MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|