282 lines
7.6 KiB
C
282 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Maxime Coquelin 2015
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* Copyright (C) STMicroelectronics SA 2017
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* Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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* Gerald Baeza <gerald_baeza@yahoo.fr>
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*/
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#define DRIVER_NAME "stm32-usart"
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struct stm32_usart_offsets {
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u8 cr1;
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u8 cr2;
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u8 cr3;
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u8 brr;
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u8 gtpr;
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u8 rtor;
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u8 rqr;
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u8 isr;
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u8 icr;
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u8 rdr;
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u8 tdr;
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};
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struct stm32_usart_config {
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u8 uart_enable_bit; /* USART_CR1_UE */
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bool has_7bits_data;
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bool has_wakeup;
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bool has_fifo;
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int fifosize;
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};
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struct stm32_usart_info {
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struct stm32_usart_offsets ofs;
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struct stm32_usart_config cfg;
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};
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#define UNDEF_REG 0xff
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/* Register offsets */
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struct stm32_usart_info stm32f4_info = {
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.ofs = {
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.isr = 0x00,
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.rdr = 0x04,
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.tdr = 0x04,
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.brr = 0x08,
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.cr1 = 0x0c,
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.cr2 = 0x10,
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.cr3 = 0x14,
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.gtpr = 0x18,
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.rtor = UNDEF_REG,
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.rqr = UNDEF_REG,
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.icr = UNDEF_REG,
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},
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.cfg = {
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.uart_enable_bit = 13,
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.has_7bits_data = false,
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.fifosize = 1,
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}
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};
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struct stm32_usart_info stm32f7_info = {
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.ofs = {
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.cr1 = 0x00,
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.cr2 = 0x04,
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.cr3 = 0x08,
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.brr = 0x0c,
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.gtpr = 0x10,
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.rtor = 0x14,
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.rqr = 0x18,
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.isr = 0x1c,
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.icr = 0x20,
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.rdr = 0x24,
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.tdr = 0x28,
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},
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.cfg = {
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.uart_enable_bit = 0,
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.has_7bits_data = true,
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.fifosize = 1,
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}
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};
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struct stm32_usart_info stm32h7_info = {
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.ofs = {
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.cr1 = 0x00,
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.cr2 = 0x04,
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.cr3 = 0x08,
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.brr = 0x0c,
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.gtpr = 0x10,
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.rtor = 0x14,
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.rqr = 0x18,
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.isr = 0x1c,
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.icr = 0x20,
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.rdr = 0x24,
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.tdr = 0x28,
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},
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.cfg = {
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.uart_enable_bit = 0,
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.has_7bits_data = true,
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.has_wakeup = true,
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.has_fifo = true,
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.fifosize = 16,
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}
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};
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/* USART_SR (F4) / USART_ISR (F7) */
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#define USART_SR_PE BIT(0)
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#define USART_SR_FE BIT(1)
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#define USART_SR_NF BIT(2)
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#define USART_SR_ORE BIT(3)
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#define USART_SR_IDLE BIT(4)
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#define USART_SR_RXNE BIT(5)
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#define USART_SR_TC BIT(6)
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#define USART_SR_TXE BIT(7)
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#define USART_SR_CTSIF BIT(9)
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#define USART_SR_CTS BIT(10) /* F7 */
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#define USART_SR_RTOF BIT(11) /* F7 */
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#define USART_SR_EOBF BIT(12) /* F7 */
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#define USART_SR_ABRE BIT(14) /* F7 */
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#define USART_SR_ABRF BIT(15) /* F7 */
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#define USART_SR_BUSY BIT(16) /* F7 */
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#define USART_SR_CMF BIT(17) /* F7 */
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#define USART_SR_SBKF BIT(18) /* F7 */
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#define USART_SR_WUF BIT(20) /* H7 */
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#define USART_SR_TEACK BIT(21) /* F7 */
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#define USART_SR_ERR_MASK (USART_SR_ORE | USART_SR_FE | USART_SR_PE)
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/* Dummy bits */
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#define USART_SR_DUMMY_RX BIT(16)
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/* USART_ICR (F7) */
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#define USART_CR_TC BIT(6)
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/* USART_DR */
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#define USART_DR_MASK GENMASK(8, 0)
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/* USART_BRR */
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#define USART_BRR_DIV_F_MASK GENMASK(3, 0)
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#define USART_BRR_DIV_M_MASK GENMASK(15, 4)
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#define USART_BRR_DIV_M_SHIFT 4
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#define USART_BRR_04_R_SHIFT 1
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/* USART_CR1 */
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#define USART_CR1_SBK BIT(0)
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#define USART_CR1_RWU BIT(1) /* F4 */
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#define USART_CR1_UESM BIT(1) /* H7 */
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#define USART_CR1_RE BIT(2)
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#define USART_CR1_TE BIT(3)
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#define USART_CR1_IDLEIE BIT(4)
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#define USART_CR1_RXNEIE BIT(5)
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#define USART_CR1_TCIE BIT(6)
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#define USART_CR1_TXEIE BIT(7)
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#define USART_CR1_PEIE BIT(8)
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#define USART_CR1_PS BIT(9)
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#define USART_CR1_PCE BIT(10)
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#define USART_CR1_WAKE BIT(11)
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#define USART_CR1_M0 BIT(12) /* F7 (CR1_M for F4) */
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#define USART_CR1_MME BIT(13) /* F7 */
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#define USART_CR1_CMIE BIT(14) /* F7 */
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#define USART_CR1_OVER8 BIT(15)
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#define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */
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#define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */
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#define USART_CR1_RTOIE BIT(26) /* F7 */
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#define USART_CR1_EOBIE BIT(27) /* F7 */
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#define USART_CR1_M1 BIT(28) /* F7 */
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#define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
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#define USART_CR1_FIFOEN BIT(29) /* H7 */
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#define USART_CR1_DEAT_SHIFT 21
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#define USART_CR1_DEDT_SHIFT 16
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/* USART_CR2 */
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#define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */
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#define USART_CR2_ADDM7 BIT(4) /* F7 */
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#define USART_CR2_LBCL BIT(8)
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#define USART_CR2_CPHA BIT(9)
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#define USART_CR2_CPOL BIT(10)
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#define USART_CR2_CLKEN BIT(11)
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#define USART_CR2_STOP_2B BIT(13)
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#define USART_CR2_STOP_MASK GENMASK(13, 12)
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#define USART_CR2_LINEN BIT(14)
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#define USART_CR2_SWAP BIT(15) /* F7 */
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#define USART_CR2_RXINV BIT(16) /* F7 */
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#define USART_CR2_TXINV BIT(17) /* F7 */
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#define USART_CR2_DATAINV BIT(18) /* F7 */
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#define USART_CR2_MSBFIRST BIT(19) /* F7 */
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#define USART_CR2_ABREN BIT(20) /* F7 */
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#define USART_CR2_ABRMOD_MASK GENMASK(22, 21) /* F7 */
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#define USART_CR2_RTOEN BIT(23) /* F7 */
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#define USART_CR2_ADD_F7_MASK GENMASK(31, 24) /* F7 */
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/* USART_CR3 */
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#define USART_CR3_EIE BIT(0)
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#define USART_CR3_IREN BIT(1)
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#define USART_CR3_IRLP BIT(2)
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#define USART_CR3_HDSEL BIT(3)
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#define USART_CR3_NACK BIT(4)
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#define USART_CR3_SCEN BIT(5)
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#define USART_CR3_DMAR BIT(6)
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#define USART_CR3_DMAT BIT(7)
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#define USART_CR3_RTSE BIT(8)
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#define USART_CR3_CTSE BIT(9)
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#define USART_CR3_CTSIE BIT(10)
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#define USART_CR3_ONEBIT BIT(11)
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#define USART_CR3_OVRDIS BIT(12) /* F7 */
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#define USART_CR3_DDRE BIT(13) /* F7 */
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#define USART_CR3_DEM BIT(14) /* F7 */
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#define USART_CR3_DEP BIT(15) /* F7 */
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#define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */
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#define USART_CR3_WUS_MASK GENMASK(21, 20) /* H7 */
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#define USART_CR3_WUS_START_BIT BIT(21) /* H7 */
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#define USART_CR3_WUFIE BIT(22) /* H7 */
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#define USART_CR3_TXFTIE BIT(23) /* H7 */
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#define USART_CR3_TCBGTIE BIT(24) /* H7 */
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#define USART_CR3_RXFTCFG_MASK GENMASK(27, 25) /* H7 */
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#define USART_CR3_RXFTCFG_SHIFT 25 /* H7 */
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#define USART_CR3_RXFTIE BIT(28) /* H7 */
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#define USART_CR3_TXFTCFG_MASK GENMASK(31, 29) /* H7 */
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#define USART_CR3_TXFTCFG_SHIFT 29 /* H7 */
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/* TX FIFO threashold set to half of its depth */
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#define USART_CR3_TXFTCFG_HALF 0x2
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/* RX FIFO threashold set to half of its depth */
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#define USART_CR3_RXFTCFG_HALF 0x2
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/* USART_GTPR */
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#define USART_GTPR_PSC_MASK GENMASK(7, 0)
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#define USART_GTPR_GT_MASK GENMASK(15, 8)
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/* USART_RTOR */
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#define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */
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#define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */
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/* USART_RQR */
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#define USART_RQR_ABRRQ BIT(0) /* F7 */
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#define USART_RQR_SBKRQ BIT(1) /* F7 */
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#define USART_RQR_MMRQ BIT(2) /* F7 */
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#define USART_RQR_RXFRQ BIT(3) /* F7 */
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#define USART_RQR_TXFRQ BIT(4) /* F7 */
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/* USART_ICR */
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#define USART_ICR_PECF BIT(0) /* F7 */
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#define USART_ICR_FECF BIT(1) /* F7 */
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#define USART_ICR_ORECF BIT(3) /* F7 */
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#define USART_ICR_IDLECF BIT(4) /* F7 */
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#define USART_ICR_TCCF BIT(6) /* F7 */
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#define USART_ICR_CTSCF BIT(9) /* F7 */
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#define USART_ICR_RTOCF BIT(11) /* F7 */
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#define USART_ICR_EOBCF BIT(12) /* F7 */
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#define USART_ICR_CMCF BIT(17) /* F7 */
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#define USART_ICR_WUCF BIT(20) /* H7 */
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#define STM32_SERIAL_NAME "ttySTM"
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#define STM32_MAX_PORTS 8
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#define RX_BUF_L 200 /* dma rx buffer length */
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#define RX_BUF_P RX_BUF_L /* dma rx buffer period */
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#define TX_BUF_L 200 /* dma tx buffer length */
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struct stm32_port {
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struct uart_port port;
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struct clk *clk;
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struct stm32_usart_info *info;
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struct dma_chan *rx_ch; /* dma rx channel */
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dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
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unsigned char *rx_buf; /* dma rx buffer cpu address */
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struct dma_chan *tx_ch; /* dma tx channel */
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dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
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unsigned char *tx_buf; /* dma tx buffer cpu address */
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u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */
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u32 cr3_irq; /* USART_CR3_RXFTIE */
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int last_res;
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bool tx_dma_busy; /* dma tx busy */
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bool hw_flow_control;
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bool fifoen;
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int wakeirq;
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int rdr_mask; /* receive data register mask */
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struct mctrl_gpios *gpios; /* modem control gpios */
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};
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static struct stm32_port stm32_ports[STM32_MAX_PORTS];
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static struct uart_driver stm32_usart_driver;
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