OpenCloudOS-Kernel/drivers/cxl
Dan Williams 75b7ae2999 cxl/mem: Validate port connectivity before dvsec ranges
In preparation for validating DVSEC ranges against the platform declared
CXL memory ranges (ACPI CFMWS) move port enumeration before the
endpoint's decoder validation. Ultimately this logic will move to the
port driver, but create a bisect point before that larger move.

Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291687749.1426646.18091538443879226995.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2022-05-19 08:50:41 -07:00
..
core cxl: Drop cxl_device_lock() 2022-04-28 14:01:55 -07:00
Kconfig PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
Makefile PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
acpi.c cxl/acpi: Add root device lockdep validation 2022-04-28 14:01:54 -07:00
cxl.h cxl: Drop cxl_device_lock() 2022-04-28 14:01:55 -07:00
cxlmem.h PM: CXL: Disable suspend 2022-04-22 16:09:42 -07:00
cxlpci.h cxl/pci: Retrieve CXL DVSEC memory info 2022-02-08 22:57:31 -08:00
mem.c cxl/mem: Validate port connectivity before dvsec ranges 2022-05-19 08:50:41 -07:00
pci.c cxl/pci: Drop wait_for_valid() from cxl_await_media_ready() 2022-05-19 08:50:40 -07:00
pmem.c cxl: Drop cxl_device_lock() 2022-04-28 14:01:55 -07:00
port.c cxl/core/port: Add endpoint decoders 2022-02-08 22:57:32 -08:00