417 lines
10 KiB
C
417 lines
10 KiB
C
/*
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* Driver for the MDIO interface of Marvell network interfaces.
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*
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* Since the MDIO interface of Marvell network interfaces is shared
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* between all network interfaces, having a single driver allows to
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* handle concurrent accesses properly (you may have four Ethernet
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* ports, but they in fact share the same SMI interface to access
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* the MDIO bus). This driver is currently used by the mvneta and
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* mv643xx_eth drivers.
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_mdio.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/wait.h>
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#define MVMDIO_SMI_DATA_SHIFT 0
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#define MVMDIO_SMI_PHY_ADDR_SHIFT 16
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#define MVMDIO_SMI_PHY_REG_SHIFT 21
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#define MVMDIO_SMI_READ_OPERATION BIT(26)
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#define MVMDIO_SMI_WRITE_OPERATION 0
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#define MVMDIO_SMI_READ_VALID BIT(27)
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#define MVMDIO_SMI_BUSY BIT(28)
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#define MVMDIO_ERR_INT_CAUSE 0x007C
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#define MVMDIO_ERR_INT_SMI_DONE 0x00000010
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#define MVMDIO_ERR_INT_MASK 0x0080
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#define MVMDIO_XSMI_MGNT_REG 0x0
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#define MVMDIO_XSMI_PHYADDR_SHIFT 16
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#define MVMDIO_XSMI_DEVADDR_SHIFT 21
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#define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26)
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#define MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
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#define MVMDIO_XSMI_READ_VALID BIT(29)
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#define MVMDIO_XSMI_BUSY BIT(30)
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#define MVMDIO_XSMI_ADDR_REG 0x8
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/*
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* SMI Timeout measurements:
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* - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)
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* - Armada 370 (Globalscale Mirabox): 41us to 43us (Polled)
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*/
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#define MVMDIO_SMI_TIMEOUT 1000 /* 1000us = 1ms */
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#define MVMDIO_SMI_POLL_INTERVAL_MIN 45
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#define MVMDIO_SMI_POLL_INTERVAL_MAX 55
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#define MVMDIO_XSMI_POLL_INTERVAL_MIN 150
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#define MVMDIO_XSMI_POLL_INTERVAL_MAX 160
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struct orion_mdio_dev {
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void __iomem *regs;
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struct clk *clk[3];
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/*
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* If we have access to the error interrupt pin (which is
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* somewhat misnamed as it not only reflects internal errors
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* but also reflects SMI completion), use that to wait for
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* SMI access completion instead of polling the SMI busy bit.
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*/
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int err_interrupt;
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wait_queue_head_t smi_busy_wait;
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};
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enum orion_mdio_bus_type {
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BUS_TYPE_SMI,
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BUS_TYPE_XSMI
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};
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struct orion_mdio_ops {
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int (*is_done)(struct orion_mdio_dev *);
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unsigned int poll_interval_min;
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unsigned int poll_interval_max;
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};
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/* Wait for the SMI unit to be ready for another operation
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*/
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static int orion_mdio_wait_ready(const struct orion_mdio_ops *ops,
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struct mii_bus *bus)
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{
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struct orion_mdio_dev *dev = bus->priv;
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unsigned long timeout = usecs_to_jiffies(MVMDIO_SMI_TIMEOUT);
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unsigned long end = jiffies + timeout;
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int timedout = 0;
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while (1) {
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if (ops->is_done(dev))
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return 0;
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else if (timedout)
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break;
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if (dev->err_interrupt <= 0) {
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usleep_range(ops->poll_interval_min,
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ops->poll_interval_max);
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if (time_is_before_jiffies(end))
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++timedout;
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} else {
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/* wait_event_timeout does not guarantee a delay of at
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* least one whole jiffie, so timeout must be no less
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* than two.
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*/
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if (timeout < 2)
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timeout = 2;
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wait_event_timeout(dev->smi_busy_wait,
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ops->is_done(dev), timeout);
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++timedout;
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}
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}
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dev_err(bus->parent, "Timeout: SMI busy for too long\n");
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return -ETIMEDOUT;
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}
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static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev)
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{
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return !(readl(dev->regs) & MVMDIO_SMI_BUSY);
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}
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static const struct orion_mdio_ops orion_mdio_smi_ops = {
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.is_done = orion_mdio_smi_is_done,
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.poll_interval_min = MVMDIO_SMI_POLL_INTERVAL_MIN,
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.poll_interval_max = MVMDIO_SMI_POLL_INTERVAL_MAX,
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};
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static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id,
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int regnum)
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{
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struct orion_mdio_dev *dev = bus->priv;
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u32 val;
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int ret;
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if (regnum & MII_ADDR_C45)
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return -EOPNOTSUPP;
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ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
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if (ret < 0)
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return ret;
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writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
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(regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
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MVMDIO_SMI_READ_OPERATION),
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dev->regs);
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ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
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if (ret < 0)
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return ret;
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val = readl(dev->regs);
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if (!(val & MVMDIO_SMI_READ_VALID)) {
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dev_err(bus->parent, "SMI bus read not valid\n");
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return -ENODEV;
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}
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return val & GENMASK(15, 0);
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}
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static int orion_mdio_smi_write(struct mii_bus *bus, int mii_id,
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int regnum, u16 value)
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{
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struct orion_mdio_dev *dev = bus->priv;
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int ret;
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if (regnum & MII_ADDR_C45)
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return -EOPNOTSUPP;
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ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
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if (ret < 0)
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return ret;
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writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
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(regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
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MVMDIO_SMI_WRITE_OPERATION |
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(value << MVMDIO_SMI_DATA_SHIFT)),
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dev->regs);
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return 0;
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}
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static int orion_mdio_xsmi_is_done(struct orion_mdio_dev *dev)
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{
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return !(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & MVMDIO_XSMI_BUSY);
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}
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static const struct orion_mdio_ops orion_mdio_xsmi_ops = {
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.is_done = orion_mdio_xsmi_is_done,
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.poll_interval_min = MVMDIO_XSMI_POLL_INTERVAL_MIN,
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.poll_interval_max = MVMDIO_XSMI_POLL_INTERVAL_MAX,
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};
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static int orion_mdio_xsmi_read(struct mii_bus *bus, int mii_id,
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int regnum)
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{
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struct orion_mdio_dev *dev = bus->priv;
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u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
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int ret;
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if (!(regnum & MII_ADDR_C45))
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return -EOPNOTSUPP;
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ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
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if (ret < 0)
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return ret;
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writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
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writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
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(dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
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MVMDIO_XSMI_READ_OPERATION,
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dev->regs + MVMDIO_XSMI_MGNT_REG);
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ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
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if (ret < 0)
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return ret;
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if (!(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) &
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MVMDIO_XSMI_READ_VALID)) {
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dev_err(bus->parent, "XSMI bus read not valid\n");
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return -ENODEV;
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}
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return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
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}
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static int orion_mdio_xsmi_write(struct mii_bus *bus, int mii_id,
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int regnum, u16 value)
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{
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struct orion_mdio_dev *dev = bus->priv;
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u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
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int ret;
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if (!(regnum & MII_ADDR_C45))
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return -EOPNOTSUPP;
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ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
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if (ret < 0)
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return ret;
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writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
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writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
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(dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
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MVMDIO_XSMI_WRITE_OPERATION | value,
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dev->regs + MVMDIO_XSMI_MGNT_REG);
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return 0;
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}
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static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id)
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{
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struct orion_mdio_dev *dev = dev_id;
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if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) &
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MVMDIO_ERR_INT_SMI_DONE) {
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writel(~MVMDIO_ERR_INT_SMI_DONE,
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dev->regs + MVMDIO_ERR_INT_CAUSE);
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wake_up(&dev->smi_busy_wait);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int orion_mdio_probe(struct platform_device *pdev)
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{
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enum orion_mdio_bus_type type;
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struct resource *r;
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struct mii_bus *bus;
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struct orion_mdio_dev *dev;
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int i, ret;
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type = (enum orion_mdio_bus_type)of_device_get_match_data(&pdev->dev);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "No SMI register address given\n");
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return -ENODEV;
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}
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bus = devm_mdiobus_alloc_size(&pdev->dev,
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sizeof(struct orion_mdio_dev));
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if (!bus)
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return -ENOMEM;
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switch (type) {
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case BUS_TYPE_SMI:
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bus->read = orion_mdio_smi_read;
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bus->write = orion_mdio_smi_write;
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break;
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case BUS_TYPE_XSMI:
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bus->read = orion_mdio_xsmi_read;
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bus->write = orion_mdio_xsmi_write;
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break;
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}
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bus->name = "orion_mdio_bus";
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snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii",
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dev_name(&pdev->dev));
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bus->parent = &pdev->dev;
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dev = bus->priv;
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dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
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if (!dev->regs) {
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dev_err(&pdev->dev, "Unable to remap SMI register\n");
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return -ENODEV;
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}
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init_waitqueue_head(&dev->smi_busy_wait);
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for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
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dev->clk[i] = of_clk_get(pdev->dev.of_node, i);
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if (IS_ERR(dev->clk[i]))
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break;
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clk_prepare_enable(dev->clk[i]);
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}
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dev->err_interrupt = platform_get_irq(pdev, 0);
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if (dev->err_interrupt > 0 &&
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resource_size(r) < MVMDIO_ERR_INT_MASK + 4) {
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dev_err(&pdev->dev,
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"disabling interrupt, resource size is too small\n");
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dev->err_interrupt = 0;
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}
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if (dev->err_interrupt > 0) {
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ret = devm_request_irq(&pdev->dev, dev->err_interrupt,
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orion_mdio_err_irq,
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IRQF_SHARED, pdev->name, dev);
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if (ret)
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goto out_mdio;
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writel(MVMDIO_ERR_INT_SMI_DONE,
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dev->regs + MVMDIO_ERR_INT_MASK);
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} else if (dev->err_interrupt == -EPROBE_DEFER) {
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ret = -EPROBE_DEFER;
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goto out_mdio;
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}
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ret = of_mdiobus_register(bus, pdev->dev.of_node);
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if (ret < 0) {
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dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
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goto out_mdio;
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}
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platform_set_drvdata(pdev, bus);
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return 0;
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out_mdio:
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if (dev->err_interrupt > 0)
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writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
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for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
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if (IS_ERR(dev->clk[i]))
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break;
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clk_disable_unprepare(dev->clk[i]);
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clk_put(dev->clk[i]);
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}
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return ret;
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}
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static int orion_mdio_remove(struct platform_device *pdev)
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{
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struct mii_bus *bus = platform_get_drvdata(pdev);
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struct orion_mdio_dev *dev = bus->priv;
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int i;
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if (dev->err_interrupt > 0)
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writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
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mdiobus_unregister(bus);
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for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
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if (IS_ERR(dev->clk[i]))
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break;
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clk_disable_unprepare(dev->clk[i]);
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clk_put(dev->clk[i]);
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}
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return 0;
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}
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static const struct of_device_id orion_mdio_match[] = {
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{ .compatible = "marvell,orion-mdio", .data = (void *)BUS_TYPE_SMI },
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{ .compatible = "marvell,xmdio", .data = (void *)BUS_TYPE_XSMI },
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{ }
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};
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MODULE_DEVICE_TABLE(of, orion_mdio_match);
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static struct platform_driver orion_mdio_driver = {
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.probe = orion_mdio_probe,
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.remove = orion_mdio_remove,
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.driver = {
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.name = "orion-mdio",
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.of_match_table = orion_mdio_match,
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},
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};
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module_platform_driver(orion_mdio_driver);
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MODULE_DESCRIPTION("Marvell MDIO interface driver");
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MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:orion-mdio");
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