Stephen Boyd 6e11940ab3 Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-samsung' and 'clk-amlogic' into clk-next ... - Make clk_ops::determine_rate mandatory for muxes * clk-renesas: clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic() clk: renesas: mstp: Convert to readl_poll_timeout_atomic() clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic() iopoll: Do not use timekeeping in read_poll_timeout_atomic() iopoll: Call cpu_relax() in busy loops clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write clk: renesas: r8a779a0: Add PWM clock * clk-determine-rate: (71 commits) clk: sprd: composite: Simplify determine_rate implementation ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_determine_rate() clk: Fix best_parent_rate after moving code into a separate function clk: Forbid to register a mux without determine_rate ASoC: tlv320aic32x4: div: Switch to determine_rate ASoC: tlv320aic32x4: pll: Switch to determine_rate clk: tegra: super: Switch to determine_rate clk: tegra: periph: Switch to determine_rate clk: stm32: composite: Switch to determine_rate clk: st: flexgen: Switch to determine_rate clk: sprd: composite: Switch to determine_rate clk: ingenic: tcu: Switch to determine_rate clk: ingenic: cgu: Switch to determine_rate clk: imx: scu: Switch to determine_rate clk: da8xx: clk48: Switch to determine_rate clk: si5351: clkout: Switch to determine_rate clk: si5351: msynth: Switch to determine_rate clk: si5351: pll: Switch to determine_rate clk: si5341: Switch to determine_rate clk: cdce706: clkout: Switch to determine_rate ... * clk-allwinner: clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux * clk-samsung: clk: samsung: add CONFIG_OF dependency clk: samsung: Re-add support for Exynos4212 CPU clock clk: samsung: Add Exynos4212 compatible to CLKOUT driver dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible * clk-amlogic: MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK clk: meson: pll: remove unneeded semicolon clk: meson: a1: Staticize rtc clk clk: meson: a1: add Amlogic A1 Peripherals clock controller driver clk: meson: a1: add Amlogic A1 PLL clock controller driver clk: meson: introduce new pll power-on sequence for A1 SoC family clk: meson: make pll rst bit as optional dt-bindings: clock: meson: add A1 Peripherals clock controller bindings dt-bindings: clock: meson: add A1 PLL clock controller bindings		2023-06-26 08:55:04 -07:00
..
Kconfig	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-02-10 10:35:16 +01:00
Makefile	clk: renesas: Add RZ/V2M support using the rzg2l driver	2022-05-06 09:38:40 +02:00
clk-div6.c	clk: renesas: div6: Implement range checking	2021-05-11 09:58:13 +02:00
clk-div6.h	We have two changes to the core framework this time around. The first being a	2017-11-17 20:04:24 -08:00
clk-emev2.c	Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next	2018-10-18 15:33:52 -07:00
clk-mstp.c	clk: renesas: mstp: Convert to readl_poll_timeout_atomic()	2023-06-05 15:41:43 +02:00
clk-r8a73a4.c	clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg	2022-06-13 11:53:18 +02:00
clk-r8a7740.c	clk: renesas: r8a7740: Remove r8a7740_cpg.reg	2022-06-13 11:53:18 +02:00
clk-r8a7778.c	clk: renesas: r8a7778: Remove struct r8a7778_cpg	2022-06-13 11:53:18 +02:00
clk-r8a7779.c	clk: renesas: r8a7779: Remove struct r8a7779_cpg	2022-06-13 11:53:18 +02:00
clk-rz.c	clk: renesas: rza1: Remove struct rz_cpg	2022-06-13 11:53:18 +02:00
clk-sh73a0.c	clk: renesas: sh73a0: Remove sh73a0_cpg.reg	2022-06-13 11:53:18 +02:00
r7s9210-cpg-mssr.c	clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag	2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c	clk: renesas: Move RPC core clocks	2022-04-13 12:27:45 +02:00
r8a774b1-cpg-mssr.c	clk: renesas: Move RPC core clocks	2022-04-13 12:27:45 +02:00
r8a774c0-cpg-mssr.c	clk: renesas: Move RPC core clocks	2022-04-13 12:27:45 +02:00
r8a774e1-cpg-mssr.c	clk: renesas: Move RPC core clocks	2022-04-13 12:27:45 +02:00
r8a779a0-cpg-mssr.c	clk: renesas: r8a779a0: Add PWM clock	2023-05-08 09:14:33 +02:00
r8a779f0-cpg-mssr.c	clk: renesas: r8a779f0: Fix Ethernet Switch clocks	2022-11-16 09:05:59 +01:00
r8a779g0-cpg-mssr.c	clk: renesas: r8a779g0: Add VIN clocks	2023-03-06 10:42:14 +01:00
r8a7742-cpg-mssr.c	clk: renesas: r8a7742: Add clk entry for VSPR	2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-02-10 10:35:16 +01:00
r8a7796-cpg-mssr.c	clk: renesas: Move RPC core clocks	2022-04-13 12:27:45 +02:00
r8a77470-cpg-mssr.c	clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)	2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c	clk: renesas: Move RPC core clocks	2022-04-13 12:27:45 +02:00
r8a77970-cpg-mssr.c	clk: renesas: r8a77970: Add Z2 clock	2023-03-10 17:07:07 +01:00
r8a77980-cpg-mssr.c	clk: renesas: r8a77980: Add I2C5 clock	2023-03-30 16:44:04 +02:00
r8a77990-cpg-mssr.c	clk: renesas: Move RPC core clocks	2022-04-13 12:27:45 +02:00
r8a77995-cpg-mssr.c	clk: renesas: r8a77995: Fix VIN parent clock	2023-03-06 10:42:14 +01:00
r9a06g032-clocks.c	clk: renesas: r9a06g032: Add a determine_rate hook	2023-06-08 18:39:29 -07:00
r9a07g043-cpg.c	clk: renesas: r9a07g043: Drop WDT2 clock and reset entry	2022-10-26 12:38:01 +02:00
r9a07g044-cpg.c	clk: renesas: r9a07g044: Add clock and reset entries for CRU	2023-01-12 17:18:48 +01:00
r9a09g011-cpg.c	clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries	2022-12-27 09:45:23 +01:00
rcar-cpg-lib.c	clk: renesas: rcar-gen3: Switch to new SD clock handling	2021-11-19 11:32:39 +01:00
rcar-cpg-lib.h	clk: renesas: rcar-gen3: Switch to new SD clock handling	2021-11-19 11:32:39 +01:00
rcar-gen2-cpg.c	clk: renesas: Zero init clk_init_data	2021-03-30 09:58:27 +02:00
rcar-gen2-cpg.h	clk: renesas: rcar-gen2: Change multipliers and dividers to u8	2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-02-10 10:35:16 +01:00
rcar-gen3-cpg.h	clk: renesas: r8a77995: Add RPC clocks	2022-04-11 12:13:13 +02:00
rcar-gen4-cpg.c	clk: renesas: r8a779g0: Add custom clock for PLL2	2023-01-24 10:11:50 +01:00
rcar-gen4-cpg.h	clk: renesas: r8a779g0: Add custom clock for PLL2	2023-01-24 10:11:50 +01:00
rcar-usb2-clock-sel.c	clk: renesas: Convert to platform remove callback returning void	2023-03-16 16:54:21 +01:00
renesas-cpg-mssr.c	clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()	2023-06-05 15:41:43 +02:00
renesas-cpg-mssr.h	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	2023-02-10 10:35:16 +01:00
rzg2l-cpg.c	clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()	2023-06-05 15:41:43 +02:00
rzg2l-cpg.h	clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write	2023-05-23 09:06:50 +02:00