345 lines
8.9 KiB
Plaintext
345 lines
8.9 KiB
Plaintext
/*
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* Device Tree Source for AMCC Makalu (405EX)
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*
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* Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "amcc,makalu";
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compatible = "amcc,makalu";
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dcr-parent = <&/cpus/cpu@0>;
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aliases {
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ethernet0 = &EMAC0;
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ethernet1 = &EMAC1;
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serial0 = &UART0;
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serial1 = &UART1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,405EX";
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reg = <0>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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timebase-frequency = <0>; /* Filled in by U-Boot */
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i-cache-line-size = <20>;
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d-cache-line-size = <20>;
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i-cache-size = <4000>; /* 16 kB */
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d-cache-size = <4000>; /* 16 kB */
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dcr-controller;
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dcr-access-method = "native";
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};
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};
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memory {
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device_type = "memory";
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reg = <0 0>; /* Filled in by U-Boot */
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};
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UIC0: interrupt-controller {
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compatible = "ibm,uic-405ex", "ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0c0 009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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UIC1: interrupt-controller1 {
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compatible = "ibm,uic-405ex","ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0d0 009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <1e 4 1f 4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC2: interrupt-controller2 {
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compatible = "ibm,uic-405ex","ibm,uic";
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interrupt-controller;
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cell-index = <2>;
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dcr-reg = <0e0 009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <1c 4 1d 4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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plb {
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compatible = "ibm,plb-405ex", "ibm,plb4";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; /* Filled in by U-Boot */
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SDRAM0: memory-controller {
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compatible = "ibm,sdram-405ex";
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dcr-reg = <010 2>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
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dcr-reg = <180 62>;
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num-tx-chans = <2>;
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num-rx-chans = <2>;
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interrupt-parent = <&MAL0>;
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interrupts = <0 1 2 3 4>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
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/*RXEOB*/ 1 &UIC0 b 4
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/*SERR*/ 2 &UIC1 0 4
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/*TXDE*/ 3 &UIC1 1 4
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/*RXDE*/ 4 &UIC1 2 4>;
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interrupt-map-mask = <ffffffff>;
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};
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POB0: opb {
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compatible = "ibm,opb-405ex", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <80000000 80000000 10000000
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ef600000 ef600000 a00000
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f0000000 f0000000 10000000>;
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dcr-reg = <0a0 5>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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EBC0: ebc {
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compatible = "ibm,ebc-405ex", "ibm,ebc";
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dcr-reg = <012 2>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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/* ranges property is supplied by U-Boot */
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interrupts = <5 1>;
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interrupt-parent = <&UIC1>;
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nor_flash@0,0 {
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compatible = "amd,s29gl512n", "cfi-flash";
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bank-width = <2>;
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reg = <0 000000 4000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0 200000>;
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};
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partition@200000 {
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label = "root";
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reg = <200000 200000>;
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};
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partition@400000 {
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label = "user";
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reg = <400000 3b60000>;
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};
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partition@3f60000 {
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label = "env";
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reg = <3f60000 40000>;
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};
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partition@3fa0000 {
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label = "u-boot";
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reg = <3fa0000 60000>;
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};
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};
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};
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UART0: serial@ef600200 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <ef600200 8>;
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virtual-reg = <ef600200>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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interrupts = <1a 4>;
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};
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UART1: serial@ef600300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <ef600300 8>;
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virtual-reg = <ef600300>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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interrupts = <1 4>;
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};
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IIC0: i2c@ef600400 {
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compatible = "ibm,iic-405ex", "ibm,iic";
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reg = <ef600400 14>;
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interrupt-parent = <&UIC0>;
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interrupts = <2 4>;
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};
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IIC1: i2c@ef600500 {
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compatible = "ibm,iic-405ex", "ibm,iic";
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reg = <ef600500 14>;
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interrupt-parent = <&UIC0>;
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interrupts = <7 4>;
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};
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RGMII0: emac-rgmii@ef600b00 {
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compatible = "ibm,rgmii-405ex", "ibm,rgmii";
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reg = <ef600b00 104>;
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has-mdio;
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};
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EMAC0: ethernet@ef600900 {
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linux,network-index = <0>;
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device_type = "network";
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compatible = "ibm,emac-405ex", "ibm,emac4";
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interrupt-parent = <&EMAC0>;
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interrupts = <0 1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*Status*/ 0 &UIC0 18 4
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/*Wake*/ 1 &UIC1 1d 4>;
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reg = <ef600900 70>;
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local-mac-address = [000000000000]; /* Filled in by U-Boot */
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mal-device = <&MAL0>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <2328>;
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rx-fifo-size = <1000>;
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tx-fifo-size = <800>;
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phy-mode = "rgmii";
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phy-map = <0000003f>; /* Start at 6 */
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rgmii-device = <&RGMII0>;
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rgmii-channel = <0>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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};
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EMAC1: ethernet@ef600a00 {
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linux,network-index = <1>;
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device_type = "network";
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compatible = "ibm,emac-405ex", "ibm,emac4";
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interrupt-parent = <&EMAC1>;
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interrupts = <0 1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*Status*/ 0 &UIC0 19 4
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/*Wake*/ 1 &UIC1 1f 4>;
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reg = <ef600a00 70>;
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local-mac-address = [000000000000]; /* Filled in by U-Boot */
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mal-device = <&MAL0>;
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mal-tx-channel = <1>;
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mal-rx-channel = <1>;
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cell-index = <1>;
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max-frame-size = <2328>;
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rx-fifo-size = <1000>;
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tx-fifo-size = <800>;
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phy-mode = "rgmii";
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phy-map = <00000000>;
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rgmii-device = <&RGMII0>;
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rgmii-channel = <1>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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};
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};
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PCIE0: pciex@0a0000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
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primary;
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port = <0>; /* port number */
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reg = <a0000000 20000000 /* Config space access */
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ef000000 00001000>; /* Registers */
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dcr-reg = <040 020>;
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sdr-base = <400>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <02000000 0 80000000 90000000 0 08000000
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01000000 0 00000000 e0000000 0 00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <42000000 0 0 0 0 80000000>;
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/* This drives busses 0x00 to 0x3f */
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bus-range = <00 3f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0000 0 0 7>;
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interrupt-map = <
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0000 0 0 1 &UIC2 0 4 /* swizzled int A */
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0000 0 0 2 &UIC2 1 4 /* swizzled int B */
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0000 0 0 3 &UIC2 2 4 /* swizzled int C */
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0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
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};
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PCIE1: pciex@0c0000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
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primary;
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port = <1>; /* port number */
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reg = <c0000000 20000000 /* Config space access */
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ef001000 00001000>; /* Registers */
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dcr-reg = <060 020>;
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sdr-base = <440>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <02000000 0 80000000 98000000 0 08000000
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01000000 0 00000000 e0010000 0 00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <42000000 0 0 0 0 80000000>;
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/* This drives busses 0x40 to 0x7f */
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bus-range = <40 7f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0000 0 0 7>;
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interrupt-map = <
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0000 0 0 1 &UIC2 b 4 /* swizzled int A */
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0000 0 0 2 &UIC2 c 4 /* swizzled int B */
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0000 0 0 3 &UIC2 d 4 /* swizzled int C */
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0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
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};
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};
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};
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